Galaxy Low Power Implementation Platform 

Comprehensive Solution for Low Power Design Implementation 

The advanced low power solution, featuring the Galaxy™ Implementation Platform, offers support for all of the low power design techniques to deliver maximum power savings. Integrated throughout, Synopsys increases productivity by providing predictable results early on in the design cycle.

With over 15 years of proven low power innovations, Synopsys continues to provide the most complete solution for addressing the latest in low power design challenges.

 

IC Compiler
IC Compiler is an integral part of the Synopsys Galaxy™ Design Platform that delivers a complete design solution


DC Explorer
Early RTL Exploration Accelerates Synthesis and P&R
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DC Ultra
Best-in-class timing, area and power QoR correlated with physical results
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Design Compiler Graphical
Extends topographical technology to predict & alleviate routing congestion
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Power Compiler
Provides complete solution for power synthesis & optimization
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DFTMAX
Adaptive scan compression for cost-effective DSM testing
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TetraMAX ATPG
Automatic test pattern generation & diagnostics for high-quality tests
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DesignWare IP
Reduce Risk and Speed Time-to-Market with High Quality IP


Formality
Comprehensive, fast, intuitive equivalence checking
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ESP-CV
Functional verification for full custom designs


Formality
Comprehensive, fast, intuitive equivalence checking
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PrimeTime
Golden timing sign-off including STA, SSTA, SI, and power analysis
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NanoTime
High-performance transistor-level STA for custom design
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PrimeRail
In-Design Rail Analysis for Place-and-Route Engineers
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StarRC
Industry leading parasitic extraction for digital and custom design
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Liberty NCX
Reference library characterization system
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Key Benefits

  • Silicon- and production-proven comprehensive multi-voltage flow with consistent interpretation of power intent
  • Provides best timing, area, power, test quality-of-results (QoR) to meet all design goals
  • MCMM throughout for better QoR, faster
  • Power-optimized clock gating and clock tree synthesis for lowest dynamic power
  • Fine-grain control over leakage optimization and recovery results in optimized use of Low-Vt Cells
  • High accuracy in-design rail analysis
  • Comprehensive power-aware formal and static verification
Ever-shrinking deep submicron process nodes allow for more functionality, but each generation is more power hungry than its predecessor. At the same time, the market demands more functionality consolidation in a single product platform. Both of these factors drive the need for adoption of more advanced low power design techniques during implementation.

Meeting power budgets for most System-on-Chip (SoC) designs today is no longer a requirement for mobile applications only. Green initiatives and the high cost of electricity have necessitated an increase in energy efficiency through implementation of low power techniques similar to those used in the mobile application space.

Reducing power has become one of the most critical challenges for chip design teams across all markets and applications. There are several mainstream and advanced low power design techniques that can be utilized to meet the stringent low power requirements of today’s designs.

The Galaxy Platform supports implementation of all of the various techniques providing optimal power savings with predictable results.