|Power Reduction Techniques|
Are they all the same for established planar, FD-SOI and finFET transistors?
Aug 07, 2014
|Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design|
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
Sep 17, 2013
|Choosing a block representation in a UPF-based hierarchical multi-voltage IC design|
This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Sep 03, 2013
|High Performance and Low Power Design: Tradeoff or Co-Existence?|
The latest EDA innovations address the "Quadrangle of Constraints" design challenge.
Nov 19, 2012
|Considerations for Writing UPF for a Hierarchical Flow|
This article details the considerations that you need to take into account when writing UPF for a hierarchical design methodology.
Apr 06, 2012
|Guest Editorial: Low Power is Everywhere|
Apr 01, 2012
|Insight Article Technology Update: Reducing Power with Advanced Synthesis |
Dec 01, 2011