Tool & Methodology Consulting 

Take advantage of chip design tools and methodologies  

PDF IconDownload Datasheet

Synopsys customers realize how important it is to maintain a leading-edge chip design environment. To maximize an investment made in Synopsys physical design tools, they understand that the faster the latest EDA technology is adopted, the more productive design teams become and the more differentiated end-products will be.

Synopsys Professional Services provides experts in Synopsys' technology-leading design tools and platforms. Benefiting from close ties to the tool developers, extensive and ongoing employee training, and a broad resume of customer project experience, Synopsys design consultants are uniquely qualified to help rapidly deploy the latest EDA tools and technology into a customer’s design flow.

Synopsys' offers the industry's leading suite of implementation and verification design tools for developing complex chips and maintaining that technology leadership means continual enhancement of products with the most advanced features for low power design, hierarchical design and emerging technology nodes - all to improve designer productivity and address the latest design challenges. Synopsys consultants help customers take immediate and full advantage of Synopsys tools’ capabilities and run time improvements, rapidly integrating them into production flows and applying them in real-time to the most critical designs.

Synopsys’ Tool & Methodology services include assistance with:

  • Migrating and customizing design scripts for new tool versions
  • Methodology consulting to deploy design methods and best practices
  • Applying new tool features through project-based design assistance, such as:

    • Design Compiler Ultra: Library-aware mapping and structuring, data path optimization, critical path re-synthesis and topographical technology for accurate correlation to post-layout timing, area and power
    • Design Compiler Graphical: Virtual global routing technology to predict wire routing congestion during RTL synthesis
    • IC Compiler: Concurrent multi-mode, multi-corner optimization, advanced clock tree synthesis including multisource clock tree synthesis and post-route optimization, physically-aware scan-chain optimization, signal integrity (SI) and Multi-Vth leakage power optimization, multi-voltage power optimization, MTCMOS leakage optimization, final stage leakage recovery, ODL and TIO for managing hierarhcial deisgn, Double Patterning Technology (DPT) and FINFET support, minimum physical impact ECO flow
    • IC Compiler Zroute Technology: Advanced routing algorithms, concurrent DFM optimizations and multithreading
    • IC Validator: In-Design physical verification
    • PrimeTime Suite: HSpice-accurate analysis, CCS modeling, automated hold fixing, ILM/ETM-based hierarchical static timing analysis, advanced on-chip variation (AOCV), crosstalk delay/crosstalk noise, IR drop analysis, SI sign-off, comprehensive power analysis extension, vector-free analysis, variation-aware statistical timing, hyperscale technology, DPT and FINFET modeling
    • VCS: SystemVerilog for design and verification using OVM,VMM,UVM, coverage analysis, advanced debug and visualization environment,

To get more information on how we can customize our services for you, please contact Synopsys Professional Services or call your local sales representative.

NewsArticlesDatasheetsSuccess StoriesWhite PapersTechnical PapersWebinars