Technical Papers 2003 

Conference Papers and Presentations 

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This paper describes a hierarchical timing closure methodology for a complex, low power, and high performance multimedia application platform. Detailed discussions of issues and solutions are given in the areas of hierarchical timing closure strategies, floor planning, hierarchical logic and physical combined optimization, and complex clock distribution and balance.
Kaijian Shi, Synopsys Professional Services
James SW Song, Pallas Yang, Minh Chau, Sandeep Aggarwal, Uming Ko, Texas Instruments, Inc.

IFIP 2003
The complexity of today's System On Chip (SoC) designs requires a faster and simpler flow and methodology for new SoC design projects. So, to get more SoCs to market faster-and less expensively STMicroelectronics Audio Division (Audio & Automotive Group) combined forces with Synopsys® Professional Services to conceive a new flow and methodology for the Audio Decoder. The collaboration will provide ST SoC design teams with a low-cost solution, by extending Synopsys' AMBA DesignWare to support STMicroelectronics' STA012.
Mauro Bosco, ST Microelectronics
Sam Bordbar, Synopsys
Sal Tiralongo, Synopsys

SNUG Taiwan 2003
IP creation and deployment has many challenges including making it configurable to fit different applications, use in multiple technologies, thorough commenting, verification, robust scripts, easy to use interface and good documentation. Synopsys offers solutions to help make IP creation and deployment more effective with it’s soft IP packaging. This paper shows how to increase IP development efficiency, repeatability and quality as well as create predictable usage and integration by the customer.
Amy Deng, Synopsys

This paper presents different techniques for managing and obtaining a low power design and gives the pros and cons for each approach.
Wen-Pin Lin, Synopsys

This paper presents different signal integrity solutions offered by both Physical Compiler and Astro. Synopsys provides complete SI solution starting with prevention during placement and routing and at Sign-off using PT-SI and Star-RCXT. Doll Lee, Synopsys

SAMOS Conference 2003
The ever increasing complexity and heterogeneity of modern System-on-Chip designs demands early consideration and exploration of architectural alternatives, which is hardly practicable on the low abstraction level of implementation models. In this paper, a system level design methodology based on the SystemC 2.0 library is proposed, which enables the designer to reason about the architecture on a much higher level of abstraction.
Manoj Ariyamparambath and Denis Bussaglia, Synopsys Professional Services
Aachen University of Technology, German Staff

A hybrid hierarchical timing closure methodology has been developed to combine strength of the subchip based hierarchical timing closure method and flat design based logic-physical combined optimization method for a 1.5 million gate, high performance and ultra-low power DSP which has been used in a number of wireless applications. The principle and the implementation details of the methodology are provided.
Kaijian Shi, Synopsys Professional Services
Graig Godwin, Texas Instruments Inc.

DesignCon-East 2003
The paper describes a clock distribution and balancing methodology for a high performance and low power ASIC design. Various issues were discussed and solutions were provided based on our experience in a low power 3G wireless application platform ASIC design. The paper focuses on critical topics such as clock phase delays & skew reduction, maximization of clock gating effects, operation mode dependent clock delay variation control, clock signal integrity assurance, and clock balance automation strategy development.
Kaijian Shi, Stewart Shankel, Synopsys Professional Services
James Song, Sandeep Aggarwal, Texas Instruments Inc.

GOMAC 2003
New circuit libraries and architectures are being developed to achieve demanding DoD signal processing ASIC performance and power objectives with low-cost, ready available technology. Re-usable cores and improved methodology will reduce development cost and schedule.
Dale Rickard, Richard Berger, Ernie Chan, BAE Systems
Steve Patton, Robert Anderson, Lockheed Martin
Richard Brown, Dennis Sylvester, Matthew Guthaus, Harmander Deogun, Univ. of Michigan
K.J. Ray Liu, Charles Pandana, Nitin Chandrachoodan, Univ. of Maryland
BrianClegg, Synopsys Professional Services

CSME 2003 (Commercialization of Military and Space Electronics Conference & Exhibition)
Military grade electronic parts are no longer readily available and weapon system suppliers have been forced to replace these parts with commercial grade parts that often times have very short product life times. This has caused a tremendous parts obsolescence problem for the supplier of electronic assemblies for military applications. Weapon system design and support costs have dramatically skyrocketed as a result and are a particular problem when the electronic assembly also contains software or firmware.
Chuck Reusnow, Lockheed Martin Missiles and Fire Control
David C. Black, Synopsys Professional Services

GSPx & International Signal Processing Conference 2003
This paper describes a systems-on-chip (SoC) design of a complex, ultra-low power and high performance open multimedia application platform for 2.5/3G wireless. The design integrates a high performance DSP core based on an ultra-low power TMS320C55x DSP and a MPU core based on the ARM®9 Microprocessor for the optimal combination of high performance with low power consumption. The system design and the SoC implementations of the platform are described in this paper.
James SW Song, Achuta Thippana, Minh Chau, Thomas Shepherd, Texas Instruments, Inc.
Kaijian Shi, Synopsys Professional Services

SNUG Europe 2003
This paper presents a methodology for power estimation and analysis of a hierarchical design during the pre- and post- synthesis /layout phases. It provides direction specific to each toolset used-Power Compiler™, Prime Power, VCS™/ NanoSim™. It also conveys experiences and lessons learned during a real design example.
James P. Flynn, Synopsys Professional Services

Now that Signal Integrity Analysis (STA) is a required activity for processes .13µ and under, it is important for design teams to develop an accurate, predictable, and repeatable methodology for dealing with Signal Integrity issues. This paper presents the results of incorporating an SI methodology into a design flow, with emphasis in lessons learned.
Devaloy Muniz, John Pedicone, Synopsys Professional Services
Greg Guiher, Northrop Grumman

Until today, hard IP was generally preferred in the IP market, mainly due to more predictive results and to an easier validation task. But the main drawback of hard IP is the lack of flexibility (in terms of specification, technological process and form factor). As a consequence, we observe an increasing need for soft IP. The challenge is to define soft IP with an associated implementation flow that enables to use soft IP, and its flexibility, with predictability similar to hard IP.
Gerard Humeau, Xavier Robert, Jehan-Philippe Barbiero, Julien Guillemain, ST Microelectronics
Gauthier Barret, Synopsys Professional Services

This presentation addresses the most significant challenges in SoC Verification. It includes a layered testbench architecture, a system for regression management and a coverage methodology.
Marko Karppanen , Petri Nivalainen, Hemendra Talesara, Synopsys Professional Services

Time to market is STMicroelectronics number one business challenge. Market requirements evolve so rapidly and the time-to- market characteristics of its business are so demanding that the company has to continually step-up the pace with which it turns out new generations of chips. Chips such as the STi5516, an addition to the highly successful OMEGA family of set-box SoCs.
Carlo Pistritto, Giuseppe Falconeri, ST Microelectronics
Sal Tiralongo, Synopsys Professional Services

Tracking Formal Verification results becomes increasingly complicated with large, hierarchical designs, multi-site design teams, and ECO processes. As each hierarchical block progresses from RTL through synthesis, floorplanning, place & route and ECO's, the original design flow must be modified on a per-block basis. Some blocks may experience a netlist ECO and corresponding RTL change, but no re-synthesis, while other block-design flows remain intact.
Greg Guiher, Northrop Grumman
John Hogans, Jeff Alderson, John Pedicone, James Flynn, Synopsys Professional Services

As industry trends of larger gate sizes and smaller geometries continue, chip-level timing closure is becoming even more of a major obstacle in taping out a design. Static Timing Analysis (STA) run times and memory requirements increase, as gate sizes increase, and signal integrity issues are more apparent as geometries decrease. Signal integrity analysis using Primetime®-SI adds additional memory requirements to STA runs because complex signal integrity computations are preformed.
Cole O'Berry, John Pedicone, Synopsys Professional Services
Greg Guiher, Northrop Grumman

SNUG San Jose 2003
In this paper, the authors describe issues encountered during the Static Timing Analysis (STA) of an ultra-low-power 3G- wireless application platform using Synopsys' PrimeTime®. The design is described with an emphasis in the description on the low-power hierarchical aspects of the design. Additionally, the issues encountered with attendant solutions are described, and a summary is provided.
James SW. Song, Satyendra R.P.Raju Datla, Yuanqiao Zheng, Texas Instruments
Stewart Shankel, Kaijian Shi, Synopsys Professional Services

This paper describes RTL-to-layout implementation of OMAP: a low-power 3G wireless-application platform. The RTL-to-layout- implementation flow and the hierarchical-placement optimization flow are presented. Issues in the areas of synthesis, floor planning, hierarchical-placement optimization, and clock distribution are discussed, and solutions are provided.
James SW Song, Minh Chau, Pallas Yang,Texas Instruments, Inc.
Kaijian Shi, Stewart Shankel, Synopsys Professional Services

DATE 2003
The timing closure of an embedded ASIC design can be challenging due to multiple requirements of chip speed, clock distribution, power consumption and reliable design integration at the chip level.
Kaijian Shi, Synopsys Professional Services

DesignCon 2003
The effect of capacitive coupling between neighboring signals in very deep sub-micron (VDSM) ASIC designs is making the analysis of delay effects caused by crosstalk a 'must have' requirement in the ASCIC sign-off process. Without considering crosstalk-induced delay effects in the sign-off process, the design team runs the risk of compromising performance or functionality.
Kwamina Ewusie, Richard Nouri, Bill Sicaras, Synopsys Professional Services

Prototyping of complex SoC designs is a challenging task. SoC design engineers need to provide maximum compatibility between ASIC and FPGA designs, while aiming at maximum prototype clock speed required by real-time critical applications. This paper covers common challenges of targeting to both ASIC and FPGA technologies, and provides solutions and guidelines to address those.
Ilmari Waljas, Synopsys Professional Services

This paper discusses clock distribution and balancing issues in a high-performance and low-power ASIC design. It also presents practical solutions to the issues, based on our experience in a low-power 3G-wireless-application platform ASIC design. The paper focuses on critical topics such as clock-phase delays and skew reduction, maximization of clock-gating effects, operation-mode-dependent clock-delay variation control, clock signal-integrity assurance, and clock-balance- automation-strategy development.
James Song, Sandeep Aggarwal, Texas Instruments, Inc.
Kaijian Shi, Stewart Shankel, Synopsys Professional Services

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