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IEEE HLDVT Conference 2002
This paper explores a novel approach to classifying, enabling and measuring testbench re-use. Six levels of testbench re-usability are presented, ranging from utility (lowest), to communication, transactor, generate/check, configuration and tests (highest). The layers provide a template for implementation and enable re-use on a layer-by-layer basis. A qualitative measure of re-use is available directly from the layered model, while a quantitative measure is available by examining the effort required to build the layers. Alex Wakefield, Bassam Jamil Mohd, Synopsys Professional Services
Vehicular Technology Conference 2002
An adaptive receiver based on Delayed Decision Feedback Sequence Estimation (DDFSE) for the EDGE (Enhanced Data Rates for GSM Evolution) system with 8PSK modulation is presented in this paper. The issues involved in pre-conditioning the signal for equalization are discussed, as well as, the design of the whitening matched filter (WMF). A special emphasis is placed on a simple structure suitable for implementation, which is robust enough to pass Third Generation Partnership Program (3GPP) standard compliance tests, including co- and adjacent-channel requirements. In addition, the optimization of the channel estimates and the computation of soft-output decisions crucial to optimize the performance of the complete chain are discussed. Results of performance simulations for various coding schemes, propagation channels and environments (reference sensitivity, adjacent-channel interference) are presented. Marc Barberis, Stefan Heinen, Pedro Guerra, Synopsys Professional Services
SNUG Boston 2002
This paper details the methodology used for the implementation of a multi-million gates chip from RTL SystemC to gates. It describes the SystemC based design methodology and guidelines for design partitioning and coding. It also describes an implementation flow using SystemC Compiler for ASIC synthesis, a SystemC & HDL co-verification environment and specific FPGA prototyping issues. The paper shares some of the results and lessons learned from the Synopsys Professional Service group's experience on customer designs implemented using SystemC. The paper will benefit the designers and verification engineers who use or plan to use SystemC RTL to implement their designs Nianfeng Li, Dinesh Jaiswal, Sachin Idgunji, Uma Mannarsamy, Damien Col, Tammy Chow, Synopsys Professional Services
The Collapsed Clock Tree Annotation method is one of the commonly used clock tree back-annotation methods that has an advantage -- expanded clock trees can be back-annotated to an original netlist. However, the method has a drawback. The back -annotated clock tree insertion delays will be lost in post-layout design optimization when any cells in the clock trees are moved or sized. To solve this problem, a CTS annotation preservation approach has been developed. The approach has been successfully applied to timing closure of a number of ASIC designs. Kaijian Shi Ph.D., Synopsys Professional Services
Pallas Yang, Texas Instruments, Inc.
This paper describes a number of timing closure techniques applied to a 210MHz & 150k gates generic DMA controller sub-chip designed to be embedded in various ASIC application chips in TI. The timing closure of the sub-chip was challenging due to multiple requirements of chip speed, clock distribution, power consumption and reliable sub-chip embedment. This paper, explains how we achieve timing closure of the sub-chip using Physical Compiler® (PC) for placement optimization. It describes in detail how to constrain clock distribution in PC to minimize clock insertion delays and how to maximize clock gating effects in order to reduce chip power consumption. Also included is how to reduce sub-chip modeling inaccuracy and risk of antenna violations at the top level where the sub-chip is embedded.Kaijian Shi Ph.D., Synopsys Professional Services
Yuwen Zou, Texas Instruments, Inc.
SNUG Europe 2002
In order to fully enable core-based design for today's systems-on-chip (SoC) developments, the ability to quickly harden soft intellectual property (IP) and then accurately model the implementation is imperative. This approach gives the designer the flexibility of soft IP with the predictability and re-usability of hard IP. John Biggs, ARM Ltd.
Alan Gibbons, Synopsys, Inc.
The ever-increasing complexity and heterogeneity of modern systems-on-chip (SoC) designs demand early consideration and exploration of architectural alternatives, which is hardly practicable on the low abstraction level of implementation models. In this paper, a system-level design methodology based on the SystemC 2.0 library is proposed, which enables the designer to reason about the architecture on a much higher level of abstraction. The goal of this methodology is to define system architectures, which provide sufficient performance, flexibility and power efficiency as required by demanding application domains -- wireless communications, broadband networking and multimedia applications. The methodology also provides capabilities for simulating multiple levels of abstraction simultaneously. This enables re-use of the simulation environment for functional verification and of the synthesizable implementation models against the abstract architecture model. Tim Kogel, Institute for Integrated Signal Processing Systems
Denis Bussaglia, Synopsys Professional Services
Increasingly, soft IP is employed to address the opposing tension between escalating design complexity and time-to-market pressures. Soft IP is key in delivering leading-edge, high-quality designs in a time-critical fashion. The work done jointly by STM, Inc. and Synopsys, Inc. on the STBus Interconnect addresses the challenges associated with the re-use of soft IP. When incorporated into the packaging framework provided by Synopsys core tools solution, the soft IP can be maximally leveraged and meet a list of requirements defined in the Blue Book. Pasquale Butta’, Alberto Scandurra, and Giuseppe F. Falconeri
Sal Tiralongo, Synopsys Professional Services
The complexity and immediacy of today's systems-on-chip (SoC) designs, determines the strategy of using soft IP cores for new SoC design projects within ST Microelectronics (ST ) Bristol. When delivering a soft IP core to a customer for physical implementation, a key parameter is the early confidence that physical implementation and timing closure are both feasible and predictable. Steve Jones, ST Microelectronics
Michael Robinson, Synopsys Professional Services
System Design Automation (SDA) 2002
The concept of the systems-on-chip (SoC) is creating many new challenges at all stages of design flow. The challenges include the modeling and verification of these SoCs as the complexity of designs increase day by day. To a large extent the target platforms used for the SoC design affect the productivity, as the requirements of the SoC design environment need to meet very complex performance objectives. Today's executable design platforms exist only at the Register Transfer (RT) Level which is too late in the design cycle and makes the simulation speed too slow. Denis Bussaglia, Manoj Ariyamparambath, Pascal Gerbaud, Synopsys Professional Services
With the increasing pressure of time to market, it is necessary to have an efficient design flow in place in order to repeatedly achieve successful designs with shorter turn-around times. Also it is important to fully test the behavior of the systems before committing to costly hardware solutions. This paper is based on the flow that is used by Synopsys Professional Services for Wireless Receivers. H. Dawid, S. Thiel, H. Elders-Boll, M. Vaupel, E. Geesmann, M. Vellachi, and M. Antweiler, Synopsys Professional Services
This paper describes the process by which Corrent Corporation, a startup specializing in the development of high-performance internet security ICs, executed the implementation of a 2.2 Million place-able instance (approx. 6 Million gate equivalent) internet security processor ASIC in a 0.15um process. Kwamina Ewusie, Synopsys Professional Services
Neel Das and Hemanshu Bhatnagar, Corrent Corporation
This paper describes recent experiences using physical synthesis tools and top-down timing and physical budgeting to complete a 1.6M gate, 0.25u ASIC. The focus of the paper is on the use of floorplanning, top-level routing, physical synthesis, and static-timing analysis tools to minimize, or remove, the need for costly back-end iterations in order to close timing on large designs. Chris Smith, Devin Bright, Synopsys Professional Services