- Optimize your testbench architecture for VMM
- Accelerate the development of a working SystemVerilog testbench
- Document your verification plan and functional coverage map
- Integrate SystemVerilog-enabled verification IP
- Quickly ramp your team’s practical knowledge of SystemVerilog by applying the latest verification methodologies on your design
With escalating system-on-chip (SoC) size and complexity, applying verification methods that rely on the writing of directed tests leads to insufficient test coverage because the number of states and test conditions is simply too large to code by hand. SystemVerilog enables new and effective verification methodologies to be deployed, such as constrained random verification that takes advantage of functional coverage technology and compute resources to provide more testing with less test code development. Automated testbenches in SystemVerilog support constrained random and other advanced verification methodologies, providing significant gains in design productivity and minimizing the risks of functional bugs.
SystemVerilog Testbench Assistance services from Synopsys help you take full advantage of the SystemVerilog language to build a scalable and reuse-oriented testbench that verifies a device under test with coverage-driven random stimulus. To ensure a high-quality design environment, Synopsys verification specialists leverage Synopsys’ VCS® verification solution as well as the Synopsys and ARM® coauthored Verification Methodology Manual (VMM) for SystemVerilog. The VMM describes techniques and best practices that enable users to create a verification environment with more testcases and more checks in less time and with less code.
Figure 1: After an initial investment in setting up the environment,
significant productivity gains can be realized with coverage-driven
random verification methodologies, with additional benefits
from the integration of verification IP into testbenches.
In addition to advancing your testbench development, working with Synopsys consultants creates an ideal environment for knowledge sharing, giving your verification engineers and designers insight into how to utilize SystemVerilog’s full testbench infrastructure, including:
- Classes and object-oriented programming
- Constrained-random stimulus
- Functional coverage
- Process control
- Inter-process communication
- Synchronization: semaphores, mailbox, enhanced events
- Dynamic and associative arrays/lists
- The new Direct Procedural Interface for connecting with C/C++ code
Figure 2: Synopsys recommends a layered testbench architecture to facilitate reuse.
The well defined blocks communicate through standard constructs,
so users can more easily plug-in their design-specific blocks.
Synopsys’ SystemVerilog Testbench Assistance offers dedicated verification specialists to help you:
- Build a VMM-compliant layered testbench architecture to take full advantage of reuse and automation
- Document a robust verification plan, including
- Methodology summary
- Functional verification requirements
- Configuration requirements
- Stimulus requirements
- Checking requirements
- Coverage requirements
- Testbench environment
- Directed and random testcase definitions
- Construct bus functional models with both drivers and monitors
- Integrate verification IP
- Build and integrate scoreboards to indicate if DUT is functioning correctly
- Write assertions
- Measure and analyze coverage data, including code, assertions, and functional coverage
- Create and modify testcases to increase coverage
Synopsys consultants utilize Synopsys’ industry-leading SystemVerilog technology, including VCS Native Testbench, which provides nativelycompiled support for SystemVerilog as well as the industry’s most comprehensive SystemVerilog-enabled VIP library. With extensive knowledge of the most advanced verification methodologies and more than a hundred SystemVerilog testbench deployments to our credit, Synopsys is uniquely capable of assisting you to meet your verification environment goals.
For more information about Synopsys’ complete portfolio of consulting and design services, including SystemVerilog Language and Methodology Jumpstart, visit http://www.synopsys.com/Services/Pages/default.aspx or contact your local Synopsys sales representative at 650.584.5000..
For more information about Synopsys’ SystemVerilog tool flow, visit www.synopsys.com/SystemVerilog.