With everything in the world getting ‘SMART' and more portable, ASIC chip sizes have grown and power consumption requirements have become more stringent. Increases in the size and complexity of today's SoC (System-on-Chip) designs have intensified the challenges of low power design optimization and verification.
With expertise in low power design methodologies, tools and techniques, Synopsys Professional Services' design consultants can help you manage your chip's dynamic and leakage power consumption. We will help you understand the inherent tradeoffs in using power-related technologies such as voltage islands, power and clock gating, multi-voltage design, dynamic voltage scaling, multiple threshold voltages, MTCMOS and IEEE 1801(UPF). With project requirements in mind, our design consultants can then assist you in deploying the latest low-power design techniques throughout the entire design flow from synthesis through functional verification and clock tree synthesis to implementation and post-route optimization. Low power considerations are a critical requirement for the optimized cores in today's complex physical designs and leveraging leading-edge EDA design tools from the Galaxy™ Low Power Implementation Platform, optimized core hardening scripts, and the Lynx Design System, Synopsys design consultants help customers meet their ASIC processor and chip-level power goals in the most efficient manner possible.
With the number and complexity of low-power design methodologies and techniques escalating, verification of designs containing these techniques has become more challenging. As a low power design moves from one operating mode to another, comprehensive power-aware verification in all of the power states is required. With their considerable knowledge of the Synopsys‘ comprehensive Advanced Low Power Verification solution, Synopsys consultants can help you deploy new technologies that deliver the required accuracy and verification coverage for power-managed designs, including voltage-aware simulation and voltage-aware static checks.
Synopsys' Low Power Design Optimization and Verification services include assistance with:
- Low power optimization and physical design implementation
- Review scripts, power constraints and design intent, and evaluate current low-power techniques and methodologies
- Recommend and deploy new low-power methodologies including appropriate use of advanced low-power standards and techniques (IEEE 1801, DVFS, voltage islands, etc).
- Develop new scripts and integrate them for project use
- Perform power analysis and/or IR drop analysis
- Low power SoC verification
- Develop low power test plan
- Customize low power verification test plan to guide simulation and coverage
- Verify low power constructs such as isolation, power switches, and register retention
- Verify protection cells added by synthesis, such as isolation cells, level-shifters, and retention registers
- Verify implementation of power network added during place-and-route
- Verify UPF description matches implemented design
Advanced Low Power Solution
To get more information on how we can customize our services for you, please contact us or call your local sales representative.