DesignWare IP White Papers 

Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-Market
This white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges. It will discuss the use of third-party IP while noting that high-quality IP alone is not enough to accelerate time-to-market with today’s SoC complexity. The paper will also discuss issues around driver software development for the IP. Finally, it will review the five major development steps in any SoC design and how third-party IP providers should be expected to help accelerate each of these steps.
Dr. Johannes Stahl, Director of Prototyping Product Marketing, Synopsys, Inc.

Real-Time Trace: A Better Way to Debug Embedded Applications
Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This whitepaper shows the benefits of debugging with ‘real-time trace’ hardware assistance, including how it can vastly reduce the amount of time needed to track down problems in the code, and introduces other benefits, such as hot-spot profiling and code coverage, offered by real-time trace systems.
James Campbell, CAE, Synopsys, Inc.; Valeriy Kazantsev, CAE, Synopsys, Inc.; Hugh O’Keefe, Engineering Director, Ashling Microsystems

Designing Application-Specific Processors for Wireless Baseband SoCs
Traditional architectures for wireless baseband applications are no longer adequate for next-generation modem standards. Supporting multiple, evolving standards in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which allows design teams to better optimize their design’s wireless baseband SoCs. This white paper describes how tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimized software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration and trade-off analysis between performance, power and area.
Bo Wu, Technical Marketing Manager, Synopsys, Inc.

A Method to Quickly Assess the Analog Front-End Performance in Communication SoCs
This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and operating modes of different components to find the optimal performance, power, area and cost for SoCs.
Manuel Mota, Technical Marketing Manager, Synopsys, Inc.

 

 


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