The multiprotocol DesignWare® Enterprise 12G PHY IP, supporting 1.25 to 12.5 Gbps data rates, enables designers to meet the growing needs for higher bandwidth in enterprise applications.
Architected to address designers’ growing performance/power trade-off challenges, the DesignWare Enterprise 12G PHY allows designers to easily integrate enterprise protocols, including PCI Express 3.0, SATA 6G, 40GBASE-KR4, 10GBASE-KR, 10GBASE-KX4 (XAUI), 1000BASE-KX, CEI-6G, CEI-11G, SGMII, QSGMII, XFI, SFI (SFF-8431), 40GBASE-CR4, 100GBASE-CR10, CPRI, OBSAI and JESD204B, into their system-on-chips (SoCs) with higher performance and up to 20% lower power consumption than competing solutions.
Learn more about Synopsys' high-speed SerDes and Data Center solutions:
SoC architects who are developing or upgrading high-speed backplanes have unique design challenges. View these seven videos to get the answers to common questions about high-performance design.