DesignWare Webinars 

Accelerate Interface IP Integration for Faster Time-to-Market
This webinar uses case studies to address the challenges of integrating IP into an SoC, optimizing IP subsystem architecture, and simplifying IP subsystem verification.
Ralph Grundler, Product Marketing Manager for DesignWare IP Prototyping Kits and IP Subsystems, Synopsys
Feb 10, 2016
 
Synopsys and TSMC Get Smart with Bluetooth for IoT SoCs
Learn about the growing IoT market trends, the required wireless connectivity and new process technologies to achieve low-power consumption and enable efficient connectivity between devices.
Manuel Mota, Technical Marketing Manager, Synopsys; Leon Chang, Program Manager, TSMC
Feb 03, 2016
 
Securing Your IoT Processor Based System
This webinar will provide insight into IoT edge device security requirements and how they can be met with an ultra-low power processor.
Angela Raucher, Product Line Manager, ARC EM Processors, Synopsys
Dec 03, 2015
 
Impact of IP Reliability, Functional Safety & Quality in Automotive ADAS SoCs
Learn about ISO 26262 and AEC Q100 standards; latency, power, reliability and process-related design challenges; and how certified IP helps ensure functional safety, reliability and quality management.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
Dec 02, 2015
 
Configure, Integrate & Prototype IP in Minutes (Mandarin)
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Qi Wang, Senior FAE, Synopsys
Dec 01, 2015
 
Modeling, Measurement, and Verification of PCI Express® 4.0 (Synopsys and Keysight)
Learn about the IBIS-AMI model & how PHY features and performance are implemented into the model. See a comparison between IBIS-AMI simulation results & silicon measurements for a 16Gbps PCIe 4.0 link.
Pegah Alavi, Senior Applications Engineer, Keysight EEsof EDA; Jim Flynn, Design Engineer, Synopsys
Oct 28, 2015
 
Automatically Generate a Software Development Kit for Your In-House Processor Using an ASIP Tool
Learn how a tool-based approach using Synopsys' ASIP Designer can shrink the time and effort required to create a fully-featured SDK and can minimize the maintenance and support effort required.
Steve Cox, Sr. Mgr. Business Development, Processor Technologies, Synopsys
Oct 27, 2015
 
Using Foundation IP in Low-Power 40nm IoT Designs (Mandarin)
This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Xueheng Ren, Senior Field Application Engineer, Synopsys
Oct 20, 2015
 
How Flexible Floating Point IP Can Be Used to Control QoR
Control your design's floating point logic using the DesignWare Foundation Cores flexible floating point format.
Alex Tenca, Principal Engineer for DesignWare Foundation Library, Synopsys
Oct 13, 2015
 
Using Foundation IP in Low-Power 40nm IoT Designs
This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Kenneth Brock, Product Marketing Manager, Logic Libraries, Synopsys
Jul 21, 2015
 
Automotive Ethernet Moving to Time-Sensitive Environments
Learn about the required network connectivity for automotive applications like ADAS and the importance of integrating Ethernet IP that is certified to be ASIL B Ready for ISO 26262 functional safety.
John Swanson, Product Line Manager, Synopsys
Jul 14, 2015
 
Configure, Integrate & Prototype IP in Minutes
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Hugo Neto, Technical Marketing Manager for IP Prototyping Kits , Synopsys
Jun 03, 2015
 
Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping
Learn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.
Charu Khosla, Staff Customer Application Engineer, Synopsys
May 19, 2015
 
Implementing Next-Generation Vision Capabilities to Enhance Your SoC Designs
Learn about the architecture of the new DesignWare Embedded Vision (EV) Processors and the open source vision tools used to program the processors to ensure efficient resource utilization.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Apr 21, 2015
 
Accelerate DesignWare IP Driver Development for ARMv8-based Designs with Virtualizer Development Kits
Understand how Virtualizer™ Development Kits (VDKs) can be used to accelerate DesignWare® Interface IP driver development and integration into a 64-bit ARMv8 Linux software stack.
Achim Nohl, Technical Marketing Manager, Synopsys
Apr 16, 2015
 
Choosing the Optimal Multiprotocol PHY IP for Your SoC
Learn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements.
Rita Horner, Sr. Technical and Product Marketing Manager, Synopsys
Apr 02, 2015
 
Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and Application Processors
Understand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Synopsys
Mar 31, 2015
 
Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2015
 
Designing SoCs for USB Type-C Products
Understand the USB Type-C specification from an SoC designer’s perspective, how to add USB Type-C to existing designs and recommendations for new SoC architectures.
Morten Christiansen, Technical Marketing Manager, Synopsys; Gervais Fong, Senior Product Manager, Synopsys
Feb 18, 2015
 
Achieving Energy Efficiency for IoT Designs
Learn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.
Ron Lowman, Strategic Marketing Manager for IoT, Synopsys
Jan 27, 2015
 
How to Optimize your Application-Specific Processor (ASIP)
Attend this webinar to gain a demonstration of the architectural exploration flow based on IP Designer, Synopsys' ASIP design tool.
Werner Geurts, CAE Manager, Synopsys
Jan 21, 2015
 
Understanding USB 3.1’s Physical, Link & Protocol Layer Changes
Get an in-depth look at the changes in the USB 3.1 specification’s physical layer, link layer, protocol layer, and hub.
Mattew Myers, Sr. Staff R&D Engineer, Synopsys
Jan 13, 2015
 
LPDDR4 Multi-Channel Architecture
Learn about connecting multiple channels of DRAM, tradeoffs in SoC floorplans, logical to physical addressing, connecting to on-chip buses, and low-power design methods for LPDDR4.
Marc Greenberg, Director of Product Marketing for DDR Controller IP, Synopsys
Dec 02, 2014
 
Simplify Sensor and Actuator Functionality for your IoT Solution
Learn how increasing system complexity as sensor fusion functions in IoT apps expand to include biometric control features can be addressed with a tightly integrated sensor and control IP subsystem.
Rich Collins, Product Marketing Manager, Synopsys
Nov 12, 2014
 
High-Speed Embedded Linux Processing on an Embedded Power Budget
This webinar will look at a new high-speed processor implementation that can bring high-performance to your Linux-based embedded designs while significantly reducing power consumption.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Nov 06, 2014
 
Ethernet in the Connected World
In the connected world, data management and robust networking is essential. Learn about new networking demands for data management between connected devices, market trends and IEEE standards.
John A. Swanson, Product Line Manager, Synopsys
Sep 23, 2014
 
How to Develop Ultra-Low Power Voice Control and Sensor Devices for Always-On IoT Apps
Learn how the efficient response and low power consumption of the ARC® EM DSP processor and Sensory TrulyHandsfree™ software solution deliver excellent performance with long battery life for IoT apps.
Paul Garden, Product Marketing Manager, Synopsys; Bernard Brafman, Vice President of Business Development, Sensory
Sep 18, 2014
 
PCI Express 4.0 & Controller Design: Veni, Vidi, Vici
This technical webinar reviews key changes in the PCI Express 4.0 specification and explains strategies for dealing with digital design challenges, handling the higher bandwidth, and more.
Richard Solomon, Technical Marketing Manager, Synopsys
Sep 16, 2014
 
FinFETs For Your Next SoC: To Move or Not To Move?
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Prasad Saggurti, Product Marketing Manager for Embedded Memory IP, Synopsys
Jul 22, 2014
 
Designing with Non-Volatile Memory for High-Volume Automotive ICs
Learn about the challenges with designing high-volume automotive ICs and the associated non-volatile memory requirements for high performance, high reliability, and optimized area.
Angela Raucher, Product Line Manager, Synopsys; Martin Niset Senior R&D Manager, Synopsys
Jul 15, 2014
 
Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design
This webinar describes the design challenges and potential advantages of using a multi-protocol 12.5 Gbps PHY that supports a wide range of data rates, features and specifications.
Rita Horner, Product Marketing Manager, Synopsys; Paul Hua, R&D Manager, Synopsys
May 15, 2014
 
Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/power/area targets, and how choosing the correct IP/methodology avoids physical design bottlenecks.
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys;Ran Snir, VLSI Director, CEVA
Apr 24, 2014
 
The Top 5 Features to Consider when Choosing a Platform for SoC Software Development
A complete, standalone platform with all the hardware and software needed for software development, debugging, and profiling will significantly accelerate code development for SoC designs.
Allen Watson, Product Marketing Manager for ARC Development Tools, Systems and Ecosystem, Synopsys
Apr 08, 2014
 
Enterprise Ethernet IP for Data Center SoC Designs
The Ethernet protocol is evolving to support faster speeds, lower power and smaller area. This webinar reviews the drivers behind the evolution and how DesignWare 40G Ethernet IP meets these demands.
John Swanson, Product Line Manager, DesignWare Ethernet IP, Synopsys
Dec 05, 2013
 
Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.
Martin Niset, Senior Product and Test Engineering Manager, Synopsys
Oct 05, 2011
 
Build low–power, high-performance mobile SoCs with complete MIPI solutions
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Hezi Saar, Product Marketing Manager, Synopsys
Jul 26, 2011
 
Using IP-XACT to Streamline SoC Design and Verification
The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.
John A. Swanson, Senior Manager, Synopsys
Mar 17, 2011
 


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