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Modern FPGA-Based Prototyping Systems Accelerate the Transition from Stand-Alone IP Block Validation to Integrated Systems

By Troy Scott, product marketing manager, FPGA-based prototyping software

FPGA-based prototypes have become a mainstream part of the systems-on-chip (SoC) design process and are now synonymous with the system validation phase of design. SoC prototyping methodologies and the application of FPGA ICs for system validation have emerged due to the changing nature of SoC development costs and the design challenges facing engineering teams. The first issue is the changing economics of chip design where the relative cost of software engineering is outpacing hardware engineering cost with each major IC process node. At the 22/20nm node, software now represents the bulk of development cost for an engineering organization. This shifting emphasis to software is driving design teams to begin software development design phase as soon as possible to maximize the number of features that can be delivered with high quality.


Figure 1: Engineering Cost Components by Semiconductor Process Node: IBS, December 2012

What are the hardware/software integration and system validation challenges that engineer and program managers face? Here’s an example of the problem areas:
  • Start software development tasks sooner
  • Reduce risk of test silicon/software integration
  • Confirm digital IP protocol compliance with real world analog PHY
  • Process high-volumes of data at high-resolution at near real time speed
  • Provide physical connections to Tx/Rx I/O
  • Display processing results to make qualitative review possible

These problems are not the sort that can be addressed easily by simulation and hardware emulation methods that are designed to solve functional verification problems applying a mix of testbench stimulus and verification IP. To a large extent these validation problems must be addressed by a prototype can run a near real time speed and support external physical interfaces. This is why FPGA-based prototypes have emerged as a distinct and essential methodology for SoC validation. FPGA-based prototypes deliver on the promise of high performance and it is not unusual to see FPGA prototypes running at more than 20 times faster than RTL circuit simulations.

Given the capacity of high-density FPGAs many SoC prototyping scenarios can be supported by 2 or fewer FPGAs. Many stand-alone IP blocks or small subsystems can fit into the available logic resources of a single FPGA. While the expansion of general purpose logic resources has been a focus of vendors of FPGA ICs, it’s the integration of high-speed serial I/Os, edge-clocks, and gearing logic that has also benefited the prototyping engineer who seeks to support the high-speed interfaces found on SoCs for high bandwidth media and communication interfaces. For example the Virtex-7 2000T FPGA features gigabit transceivers (GTX) capable of up 12.5 Gb/s line rates and interface blocks for PCI Express compliance.

How Prototyping System Modularity Eases IP Block Integration
Many design organizations have a charter to maximize module and IP reuse to avoid replicated effort and proliferation of functional blocks. SoC design reuse and integration of pre-designed cores is a large part of how design teams can achieve such high productivity and this is reflected in the way FPGA-based prototypes are applied to the validation problem. Figure 2 illustrates a common practice by design teams to employ various capacity prototypes for individual IP block validation that are then integrated for SoC subsystem validation. A central CAD/IP department may have responsibility for IP block qualification with key physical interfaces (PHYs) and the on-chip bus fabric and then deploy the “certified” IP to the wider organization for integration into particular end-product projects as a complete sub-system. This progression of block validation through a full system validation was a big influence on the Synopsys R&D team responsible for the design of the Synopsys HAPS-70 System for FPGA-based prototyping.


Figure 2: FPGA-Based Prototype Scalability for IP Block through System Validation

Synopsys DesignWare IP R&D teams who develop cores like MIPI, HDMI, and USB IP face the same distribution issues as Synopsys customers and must comply with security and license restrictions but at the same time provide an easy way to integrate and validate IP blocks. The Synopsys HAPS series has been a vehicle for internal validation, protocol compliance testing at plug-fest events, and distribution of example implementations to customers for several years. An organization may “publish” IP as raw RTL source, hardened into FPGA-based hardware, or deployed as FPGA device program/bitstream images. Each has advantages and disadvantages and a modern FPGA-based prototyping system like HAPS-70 supports IP variations no matter the degree of hardening. The first off-the-shelf DesignWare IP implementations using the new HAPS-70 series are projected for availability in the fourth quarter of 2013.

The HAPS-70 system is the most modular and I/O intensive system yet designed by Synopsys after several generations of PCB, connector, and electromechanical refinements made over the years. To address the spectrum of capacity demands HAPS-70 is offered in nine different configurations from 12M to 144M ASIC gates of capacity. The HAPS-70 S24 shown in the photo below is comprised of two PCB modules each with a single Xilinx Virtex-7 2000T device.


Figure 3: Synopsys HAPS-70 S24: A 2-FPGA, 24 Million ASIC Gate Capacity FPGA-based Prototyping System

Sub-systems like the power modules and distribution of clock and reset circuits are implemented into boards mounted perpendicular to the FPGA host PCB modules to minimize route congestion to connectors and provide the best signal integrity characteristics. The cage-like framework is designed to provide mechanical stability when the system is stacked or assembled into racks and is open to encourage air flow and cable access.

The custom-designed connectors on the topside of each module correspond directly to the I/O bank organization of the 2000T device. Flexible cables provide connectivity among system components. This symmetry of FPGA I/O banks, connectors, and PCB modules lends itself to reuse of a prototype plan for an IP block as it moves from stand-alone validation to a fully integrated system. Pin-out, optimization options, implementation scripts, and daughter board PHYs are easily migrated from the lower capacity systems to the higher capacity ones when integration is required.

Prototype System Connectivity Enables In-Context IP Validation
FPGA-based prototype connectivity is an important feature that opens the door to a variety of use scenarios that enable earlier bring-up and more complete system integration prior to silicon availability. FPGA-based prototypes that support connectivity to other prototyping tools running remotely on a workstation enable system or “hybrid” prototypes. Hybrids allow a prototyping engineer to mix and match modeling solutions to get the best out of available resources and increase the realism of a validation scenario.

Figure 4 is an example of a design partitioned between a virtual, SystemC/TLM-based prototype and an FPGA-based prototype. This “hybrid” scenario is enabled with a transaction level link to provide system coherency between a loosely timed model and cycle-accurate hardware. The ability to run a cycle-accurate SoC block in FPGA hardware at high performance is attractive as a companion to virtual prototype simulations incorporating embedded CPUs running at very high MIPS performance executing a firmware stack, embedded OS, and an application software layer.


Figure 4: Example of a SoC Design Partitioned Between Virtual and FPGA-Based Prototypes

The motivation for design teams to adopt hybrid prototypes is often rooted in the desire to employ virtual platforms for performance and power analysis but the overall modeling effort required to incorporate the company’s proprietary IP is considered high risk. The FPGA-based prototype allows use of existing RTL blocks to be combined with an off-the-shelf virtual prototype. In this way model resources for the latest generation of a processor subsystem are mixed with familiar, in-house RTL.

The validation methodology for stand-alone IP blocks and system integration has had a big influence on the architecture of Synopsys’ latest generation of FPGA-based prototyping solution. The HAPS-70 Series combines an I/O intensive, modular system with high-bandwidth connectivity to a host computer to help accelerate the availability of prototypes for software development, silicon and software integration testing, and IP validation with real world I/O. SoC design teams who adopt DesignWare IP have a path to make prototypes available as soon as possible by using the HAPS series since it is often the same system used internally by Synopsys R&D groups.

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