High-quality, Silicon-proven DesignWare IP Solutions for Advanced SoC Designs
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Embedding Vision in Next-Generation SoCsLearn about a new class of embedded processors, designed specifically for embedded vision, that offer very high vision performance at the low cost and power-consumption levels required for embedded applications.
DesignWare Hybrid IP Prototyping Kits for Prototyping, Software Development & Integration in 64-Bit ARM Processor-Based DesignsUnderstand a new approach to IP development that bundles all necessary software and hardware components to offer the benefits of virtual and FPGA-based prototyping.
Multicore Design Using ASIPs: Blending Performance and Efficiency with ProgrammabilityFind out how to achieve the best balance of performance and power for your multicore SoCs using application-specific instruction-set processors (ASIPs) with efficient architectural exploration capabilities.
Understanding Your Power Profile from RTL to Gate-level ImplementationLearn how to optimize for dynamic power with switching activity information as well as how to identify and reduce differences in the RTL and gate-level-based switching activity power profiles after synthesis.
25G Ethernet in the Connected WorldFind out why 25G Ethernet is the logical standard to implement for a robust and cost-effective data connectivity solution.
ARC Zone: ARC EM Processors for Complex IoT DesignsLearn how ARC EM processors address the increasingly demanding power and performance needs of the IoT market.
In-Depth White Papers
Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-MarketThis white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges.
Ethernet in the Connected WorldThis white paper outlines the latest networking trends across some of the key market sectors including automotive, the connected home and data centers, and explains how Ethernet is relevant to each.
Demystifying the HDCP 2.2 Authentication ProcessThis paper explains HDCP 2.2 which is the latest generation content protection protocol.
Designing Application-Specific Processors for Wireless Baseband SoCsThis white paper describes how tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimized software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration and trade-off analysis between performance, power and area.