Chip Design Solutions Seminar 

 

March 11, 2014
Hotel Mercure, Montigny Le
Bretonneux, France

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Overview
This deeply technical event provides a forum to discover I-2013.12, the latest release of Design Compiler, Power Compiler, PrimeTime®, Formality , DFTMax® and recently introduced DC Explorer. The seminar is designed to ensure that you achieve the highest value and productivity from your Synopsys tool investment. The latest release brings new capabilities and techniques to improve performance and predictability. You will learn about new features and how to utilize them effectively to increase design implementation productivity and achieve performance, power and area goals.

We are also very pleased to welcome Marco Casale-Rossi, Product Marketing Manager at Synopsys. Mr. Casale-Rossi will make a keynote speech on "Advanced Designs at Every Nodes".

Who Should Attend
Design engineers and managers willing to get full advantage of Synopsys last release of Design Compiler, PrimeTime®, Formality and DFTMax®.

Agenda

TimeTopic
11:00 - 11:15 Welcome Participants
11:15 - 11:45Advanced Designs at Every Nodes
11:45 - 12:30RTL Synthesis, Power Compiler Update and DC-Explorer Introduction
12:30 - 13:15Lunch Break (Lunch included)
13:15 - 14:00Performance and Capacity Improvement on Formality and Primetime
14:00 - 15:00 DFTMAX Compression & TetraMax ATPG Update. Introduction of our new DFTMAX-Ultra Product
15:00 - 15:15 Wrap Up and Q & A Session

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