|Accelerate Development of Powertrain ECUs with Virtual Hardware|
This 60-minute Webinar will provide an overview of virtual hardware ECUs and how to integrate them into the automotive system development process to manage these challenges.
Marc Serughetti, Business Development, Synopsys, Inc.
Jun 21, 2016
|Better Testing Through Automation and Continuous Integration with Virtualizer Development Kits|
This webinar introduces how simulation-based Virtualizer Development Kits are the perfect technology to enable the integration and testing of hardware dependent software in a continuous manner.
Victor Reyes, Technical Marketing Manager, Synopsys
Apr 13, 2016
|Optimizing Quality-of-Service (QoS) with Interconnect and Memory Subsystem Analysis|
Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with deep, system-level analysis.
Pat Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys; Alexis Boutillier, Senior Corporate Applications Engineer, Arteris
Nov 19, 2015
|Software is eating the World: End-to-End Prototyping to the Rescue|
Co-hosted by Chris Rommel of VDC, this webinar will explore the value between prototyping methods and their benefits for enabling early architecture exploration, software development, hardware-software integration and system validation.
Tom De Schutter, Senior Product Marketing Manager, Synopsys; Chris Rommel, Executive Vice President, IoT& Embedded Technology, VDC
Nov 04, 2015
|Optimize DDR Memory Subsystem Efficiency With Synopsys Platform Architect|
The Synopsys DesignWare Enhanced Universal DDR Memory Controller (uMCTL2) provides sophisticated features to optimize DDR memory efficiency for your application while managing quality of service for individual transaction streams. The tools and techniques demonstrated in this session have been shown to produce a more optimal DDR controller configuration, improving memory bandwidth while avoiding the risk of over-design. A case study illustration will show how you can optimize the address mapping, clock frequency, and quality of service configuration for your SoC application to increase DDR memory efficiency up to 20%.
Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys, Inc.; Tim Kogel, Solution Architect, Synopsys, Inc.
Jun 05, 2015
|Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping|
Learn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.
Charu Khosla, Staff Customer Application Engineer, Synopsys
May 19, 2015
|Accelerate DesignWare IP Driver Development for ARMv8-based Designs with Virtualizer Development Kits|
Understand how Virtualizer™ Development Kits (VDKs) can be used to accelerate DesignWare® Interface IP driver development and integration into a 64-bit ARMv8 Linux software stack.
Achim Nohl, Technical Marketing Manager, Synopsys
Apr 16, 2015