Formal Equivalence Checking
STMicroelectronics: Successful Last-minute Functional ECO Implementation with Formality Ultra
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late.
Kailash Digari, Group Manager CPU-GPU design, STMicroelectronics; John Lehman, Senior CAE Manager, Synopsys
Feb 05, 2015

LSI's Experience: New Formality Ultra Speeds Functional ECOs
Learn how Formality Ultra uses innovative matching and verification technologies to help designers cut in half the time they spend implementing manual ECOs late in the design cycle. Cason Kolb, Principal Design Engineer at LSI will describe their methodology for implementing and verifying functional ECOs during the different stages of the design cycle, the issues they face, and how Formality Ultra has helped speed their ECO implementation cycles.
Cason Kolb, Principal Design Engineer, LSI; Mitchell Mlinar, R&D Group Director of Formal Verification, Synopsys; and Mark Patton, Sr. Product Marketing Manager for Formality, Synopsys
Aug 08, 2013

Verilog-to-Verilog Equivalence Checking Using ESP
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013

Meet Your Schedule with New ECO Verification and Other Enhancements in Formality
Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.
Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011

Using ESP-CV for Faster Redundancy Verification in Memory Designs
Learn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.
Dave Hedges, CAE, Implementation Group, Synopsys; Clay McDonald , R&D Manager, Implementation Group, Synopsys
Jan 19, 2011

Successful Equivalence Checking of Highly Optimized DC Ultra Designs
Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.
Mitchell Mliner, Synopsys
Apr 21, 2009