Accelerated Power Analysis and Verification with Synopsys Verdi Technologies
In this webinar, discover how native integrations of Verdi design debug technologies with Synopsys’ power analysis and verification solutions help catch power-related bugs earlier and faster. The industry-leading Verdi platform couples powerful tracing techniques with unique source code and schematic browsers, enabling teams to quickly debug low power issues in RTL or netlist designs, as well as in the UPF power intent specification. These specialized power-aware debug capabilities accelerate low power verification and ensure successful delivery of intended low power features.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Ankush Bagotra, Staff Engineer, Verification Group
Nov 08, 2016

Formal Debug: Achieving Faster Root Cause Analysis of Formal Results with VC Formal and Verdi
Based on years of hands-on experience and the latest debug features of VC Formal with Verdi, this webinar will give a practical guide to various debug techniques for analyzing formal verification results that will enable verification teams to get the most out of integrating formal verification into their flow. Using debug challenges such as assertion failures and sequential equivalence mismatches this webinar will guide users on the fastest way to a resolution. It will also show Navigator - a powerful new debug solution in Verdi – that allows quick waveform based what-if analysis on design functionality without any need for a testbench environment or assertion expertise.
Prapanna Tiwari, Senior Manager, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D. Formal Verification CAE Manager, Synopsys
Sep 14, 2016

Thinking ‘Outside the Waveform’ – Boosting Design Debug Productivity with Verdi
In this Synopsys webinar, we will show how you can cut your debug time in half with innovative Verdi design debug techniques. Specifically, you will learn how Verdi enables you to quickly explore, visualize and debug complex, and even unfamiliar designs; how you can quickly root-cause and debug simulation failures with Verdi debug techniques such as temporal flow view, automated X-tracing, assertion analyzer etc; and how Verdi’s unified debug platform extends the intuitive and familiar Verdi debug use-model to natively integrated Synopsys static and formal verification solutions.
Vaishnav Gorur, Product Marketing Manager, Verification Group, Synopsys; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys
Sep 13, 2016

Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug (Part 2 of 4)
In this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent. Specifically, you will learn how visualization of the power architecture can help identify power strategy and connectivity issues upfront; how to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL; how to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Aug 31, 2016

Time-travel in a SystemVerilog/UVM world – Interactive Testbench Debug Unleashed!
In this Synopsys webinar, we will show how interactive debug is ushering in a new era in testbench debug. Specifically, you will learn: how interactive and reverse interactive debug capabilities allow you to quickly root-cause and debug simulation failures; how what-if analysis improves TB debug efficiency by combining diagnosis and cure into a single step; how to navigate and effectively debug a UVM-based testbench
Vaishnav Gorur, Product Marketing Manager, Verification Group; and Mansour Amirfathi Sr. CAE Manager, Verification Group, Synopsys, Inc.
Jul 20, 2016

Double the Value - Accelerated SoC Verification AND Earlier Software Bring-up with Verdi HW SW Debug
In this webinar, we will show how simultaneous, synchronized views of design behavior at the software and hardware levels helps engineers at both levels debug efficiently and effectively. We’ll demonstrate how the Synopsys Verdi HW SW Debug solution seamlessly combines the industry-leading Verdi hardware debug with Eclipse-based software debug to provide a simple, yet powerful unified debug environment. Further, we will show how the solution is adapted easily to different processor core families including custom cores, as well as how it scales to debug multiple cores on a single SoC. Overall, these techniques will enable better SoC verification, accelerate software bring up and help achieve faster time-to-market.
Vaishnav Gorur, Product Marketing Manager, Synopsys, Inc. Alex Wakefield, Engineer, Synopsys, Inc.
Jun 15, 2016

Making Coverage Closure SMARTer with Verdi – A Primer on Verification Planning and Coverage Modeling
In Part I of a multi-part webinar series on Verification Planning and Coverage, we will focus on how verification planning using Verdi Coverage can help make your coverage closure goals SMART. We’ll start with a demonstration of how to create an executable verification plan from design specifications and how to structure it based on specific features, functions and design modes that need to be verified. We will then discuss the formulation of a meaningful coverage model that takes into account structural and functional coverage, as well as the different sources of coverage information. Finally, we’ll show how the verification plan acts as a centerpiece and ties together the verification data with the spec, helping provide actionable metrics to drive verification closure.
Vaishnav Gorur, Product Marketing Manager, Verification Group & Bart Thielges CAE, Coverage and Planning, Verification Group, Synopsys
May 18, 2016

Bridging the Gap in Mixed-Signal Debug: Introducing Synopsys' NEW Verdi Advanced AMS Debug Solution
In this webinar, we will demonstrate how Synopsys' new Verdi Advanced AMS debug solution, based on the market-leading Verdi SoC debug platform, delivers groundbreaking co-simulation debug for both analog and digital engineers, as well as system integrators.
Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys; Vaishnav Gorur, Product Marketing Manager, Verification Group, Synopsys
Mar 15, 2016