90nm Generic Library 

Synopsys 90nm Generic Library for Teaching IC Design 

The Synopsys 90nm Generic Library is designed for use in teaching microelectronic design. When used with the latest Synopsys EDA tools it enables students to use a more complete design flow and to master today's advanced design methods, such as low power.

90nm Generic Library Basics
  • Optimized for low power design

  • Optimized for use with Synopsys EDA software tools

  • Requires Synopsys university EULA and license addendum

  • Not designed for fabrication

90nm Generic Library Content

Technology Kit
The Technology Kit includes a databook and user guide, symbols, .lib, Verilog and VHDL simulation models, DRC and LVS decks, HSPICE netlists, extracted C/RC netlists, GDSII layout views, LEF files, generic SPICE models, fram views, layout views and runset files.

 Digital Standard Cell Library
The Digital Standard Cell Library consists of 340 cells to optimize the IC design. The library includes typical miscellaneous combinational and sequential logic cells for different drive strengths. It has all the required deliverables for low power design including support for IC designs with different core voltages to minimize dynamic and leakage power.

 I/O Standard Cell Library
The I/O Standard Cell Library consists of 50 standard and 3 special I/O cells: digital, analog, power/ground pads for different loads and miscellaneous cells. The library is designed for 1.2V/2.5V operation with a process technology of 1P9M 1.2V/2.5V and an operating frequency of 100 MHz. The library is provided in two versions: wire-bond and flip-chip.

Memories include 35 medium-sized RAMs (SRAMs). They are synchronous dual-port with write enable, output enable, and chip select on each port. They have the same architecture and vary in size.

Phase Locked Loop (PLL)
The Phase Locked Loop (PLL) clock multiplier circuit can generate a stable, high-speed clock from a slower clock signal. It has 3 operating modes: normal, external feedback and bypass.

The 90nm Generic Library contains 21 megacells for OpenSPARC and 15 megacells for IBM PowerPC 405 that are needed to fully implement the processors in a design. Additionally, two low-power designs (ChipTop and Orca) and two sample designs for OpenSPARC T1 and PowerPC 405 are also included.

OpenSPARC megacells are memory cells (SRAMs and CAMs) that are needed to fully implement the OpenSPARC processor. These megacells are designed using the 90nm Generic Library.

ChipTop is a processor architecture that features the Unified Power Format (UPF) for advanced low power designs. This reference, with included memory blocks, can be used with the 90nm Generic Library and design tools to understand the implementation of low power design methodologies and design for low power. The Orca design contains one functional block of the Orca processor. This reference can be used with the 90nm Generic Library to understand the basic design steps when using logical (DC) and physical (ICC) design tools.

The 90nm Generic Library is now available in Members Only for Synopsys University Program members to download. You must have a valid SolvNet ID and password to access. To request support for the 90nm Generic Library, contact us.

"I would recommend the Synopsys 90nm Generic Library to any faculty or university looking for a library to develop complex ASIC's or SoC designs. The integration of this library with Synopsys tools has enabled our students to develop a deeper understanding of design methodologies and physical design, which has given them the ability to implement complex designs."
Dr. Ramin Roosta, Professor of Electrical and Computer Engineering, California State University, Northridge

"It is great to know that the 90nm Generic Library from Synopsys is enhanced to work seamlessly with the industry-leading, open-source 64-bit Chip Multi-threading (CMT) microprocessor designs from Sun Microsystems. This interoperability of the technology library with the OpenSPARC design will enhance the state-of-the-art research in the areas of logic synthesis, VLSI design, and layout design, among other things."
Durgam Vahia, OpenSPARC Engineering Manager, Sun Microsystems

"We have been using the Synopsys 90nm Generic Library for synthesis and SDF-based simulations. We believe that the core and the pad libraries implementation is excellent - free of errors and rich in functionality."
John Michael Williams, Senior Faculty, Silicon Valley Technical Institute

"The libraries were successfully used to perform model checking-based verification with Formality; and also the schematic version was successfully used to perform synthesis for different combinational and sequential designs. They will be very valuable for research as well as teaching.”
Ehat Ercanli, Assistant Professor of Electrical Engineering & Computer Science, Syracuse University

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