SNUG Taiwan 2013 Proceedings

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Complete Proceedings

Speeches
Welcome and Synopsys Keynote
Accelerating Innovation in the Era of Exponentials
Author(s): Manoj Gandhi, Senior Vice President & General Manager, Verification Group - Synopsys

User Papers and Presentations
TA1 - HPC Implementation and Panel
Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow
Author(s): Tim Whitfield - ARM
Presentation

TA2 - Test/IP
DFTMAX with Serializer Architecture for I/O Limit
Author(s): Liu Jia Ping, Phison
Presentation

Era of IP
Author(s): Dan Kochpatcharin, TSMC

Memory Repair Solution With Synopsys SMS
Author(s): Karl Chang, GUC
Presentation

Port Limit Solution - JTAG Base Test Mode Decoder
Author(s): Chingtze Kao, Faraday
PaperPresentation

TA3 - Circuit Simulation
CustomSim Native IR/EM Solution
Author(s): Isabel Wang, TSMC
Presentation

Experience Sharing on Improving Simulation Time With Power Generator Circuit
Author(s): Yu-Sheng Yang, Winbond
Presentation

Mixed-Signal Design Verification Using Co-simulation With VCS-XA
Author(s): Bruce Chiu, KeyAsic
PaperPresentation

TA4 - Verification
A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests (Best Paper Award)
Author(s): Richard Tseng, Qualcomm
PaperPresentation

Does Power State Table Matter in Low Power Verification? (Best Paper Award)
Author(s): Shang-Wei Tu, MediaTek
PaperPresentation

Macro Power Aware Simulation Dilemma: UPF or DB
Author(s): Kaowen Liu, MediaTek
PaperPresentation

TB1 - HPC Implementation
Rectilinear Shape Floorplan and High Density Mali 400 Design with TSMC 28nm HPM process
Author(s): Webber Tseng, Novatek
Presentation

TB2 - Static Timing Analysis
Achieving Timing Closure on Hundred Million Gates SoC Design with ETM & ILM (Best Paper Award)
Author(s): Chi-Chia Yu - Faraday
PaperPresentation

IDEA: Innovative AOCV Design Flow with Efficiency and Accuracy
Author(s): Lancer Chen, Faraday
PaperPresentation

TB3 - IP and Ecosystem
UMC Advanced IP - SOC Design
Author(s): Ted Kao, UMC

TB4 - VIP/Verification
Migrate from DWVIP to Discovery VIP
Author(s): Debra Lin - MediaTek
PaperPresentation

WA1 - HPC and Advanced Technology
Implementation Experience Sharing with UMC 28HLP
Author(s): Ko Wen Wu - UMC
Presentation

WA2 - Synthesis
DC-Explore Experience Sharing
Author(s): Cheng Kai Huang - Ali
Presentation

Fast And Reliable PPA (Power/Performance/Area) Exploration by DC Explorer
Author(s): Der-Hua Meng - Realtek
PaperPresentation

WA3 - System
Experiences on System Integration with the CoStart for VDKs
Author(s): Louis Huang - ITRI
Presentation

WA4 - Custom Design Using Laker
Laker CDPR (Custom Design Place and Route) on DRAM
Author(s): Frank Yu - NTC

LakerBlitz - Chip Level Layout Editor
Author(s): Hsin-Po Wang - Synopsys
Tutorial

TSMC iPDK Update
Author(s): CW Wei - TSMC

WA5 - Debugging with Verdi
Create Power Intent and Verify Power Policy by Verdi3
Author(s): Chunyi Lin, MediaTek
Presentation

WB1 - Physical Implementation
Routing a Synopsys DDR PHY’s Matched Pair Signals Using Galaxy Custom Router and ICC (with Co-Design), Within Lynx
Author(s):
Tutorial

Time-to-Result Using Lynx on ARM Cortex A9-based SoC Design with UMC40LP
Author(s):
Tutorial

WB3 - Emulation and FPGA-Based Prototyping
Emulator Virtual Platform Design Methodology
Author(s): Josh Hsu - MediaTek

WB4 - Custom Design Using Laker
Laker FPD Application on e-Paper Design
Author(s): Chun-Wei Chang - Eink
Presentation

UMC iPDK Program: Development and Validation
Author(s): Anderson Huang - UMC

WB5 - Debugging with Verdi
Exploring Protolink: Effective Debugging from Firmware to Hardware
Author(s): Owen Chang - Sonix
PaperPresentation

Welcome and Synopsys Keynote
Accelerating Innovation in Electronics That Impact Everything, Everyone, Everywhere
Author(s): Paul Lo, Senior Vice President & General Manager, Analog/Mixed Signal Group, Synopsys

Tutorials
TA3 - Circuit Simulation
A Practical Look at Current Analysis in FastSpice
Author(s): Joe Huang, Synopsys
Tutorial

TA4 - Verification
VCS for Best Performance
Author(s): Alvin Chen, Synopsys
Tutorial

TB2 - Static Timing Analysis
Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Author(s): Brad Lee - Synopsys
Tutorial

Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff
Author(s): Brad Lee - Synopsys
Tutorial

TB3 - IP and Ecosystem
Considerations for Timing Budgets for DDR4 Interfaces
Author(s): William Chen - Synopsys

HDMI 2.0 & MHL 2.0: The Future of Multimedia Connectivity
Author(s): Manmeet Walia - Synopsys

TB4 - VIP/Verification
Achieving Performance Verification of ARM Processor-based SoCs Optimizing and Validating the Performance of Your AMBA® based Interconnect
Author(s): Tom Lin - Synopsys
Tutorial

HW/SW Verification and Debug with VCS and Verdi3
Author(s): Alex Wakefield - Synopsys
Tutorial

WA2 - Synthesis
Formality-Ultra
Author(s): Richard Su - Synopsys
Tutorial

WA3 - System
The Design of Embedded Vision Systems
Author(s): Jiff Kuo, Synopsys
Tutorial

WA4 - Custom Design Using Laker
Advanced-Node Layout Requirements
Author(s): Lucas Chen - Synopsys
Tutorial

WA5 - Debugging with Verdi
How do you Debug Power Related Issues? – A Methodology for Low Power Debug
Author(s): Archie Feng - Synopsys
Tutorial

Realize Your Own Ideas with Rich APPs Inside Verdi's VIA Toolbox
Author(s): Rich Chang - Synopsys
Tutorial

WB1 - Physical Implementation
Design with Non-Planar CMOS and Double-Patterning
Author(s): Synopsys
Tutorial

WB3 - Emulation and FPGA-Based Prototyping
Complex SoC Prototyping Using Xilinx Virtex 7 Based HAPS-70 Systems
Author(s): Michael Posner, Jay Chiang - Synopsys
Tutorial

Quick FPGA Prototype Platform Bring-up and Design Debug
Author(s): Freddy Lin - Synopsys
Tutorial

WB4 - Custom Design Using Laker
iPDKs: A Thriving PDK Standard
Author(s): Jingwen Yuan - Synopsys
Tutorial

Powerful and Comprehensive Devices in Laker
Author(s): Lucas Chen - Synopsys
Tutorial

WB5 - Debugging with Verdi
Customer Case Study: Validation of ARM Systems using FPGAs and ProtoLink
Author(s): Howard Mao - Synopsys
Tutorial

Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs
Author(s): Alex Wakefield - Synopsys
Tutorial

Verdi Transaction Based Debugging for SoC Designs
Author(s): Rich Chang - Synopsys
Tutorial

Panel Presentation
TA1 - HPC Implementation and Panel
HPC Panel - Achieving Optimum Results on High-Performance Processor Cores
Author(s): Moderator: Erik Olson, Synopsys, Panelists: Tomoyasu Kitaura, - Fujitsu Krishna, Kant Verma - Qualcomm, Naveen Raina - ST, Joe Walston - Synopsys

Combo
TB1 - HPC Implementation
Part 1: Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Author(s): Craig Tou - ARM, Dale Lomelino - Synopsys
Tutorial

Part 2: Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Author(s): Craig Tou - ARM, Joe Walston - Synopsys
Tutorial

Part 3: Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor
Author(s): Craig Tou - ARM, Joe Walston - Synopsys
Tutorial