Call for Papers is Now Closed.
If you have used Synopsys technology to overcome difficult design issues and to accelerate your innovation, the SNUG community wants to hear from you!
Share your experience using Synopsys tools and IP at the 2017 Synopsys Users Group (SNUG), Silicon Valley. SNUG brings together more than 2500 Synopsys users, technologists and industry experts for Silicon Valley’s largest technical conference devoted to the challenges of electronic design and verification.
As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you will be eligible for significant cash awards (please check your company’s gift acceptance policy).
The call for papers is open September 13 – November 4, 2016. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by November 10, 2016.
We have a preliminary list of topics to get you started, but don’t let that limit your ideas or innovation in your submission:
- Analog and Mixed-Signal Simulation (SPICE, FastSPICE)
- Advanced Application Methodologies (ARM, Graphics/GPUs, Processors)
- Advanced Design Methodologies (High Performance, Low Power, Area Optimization, Time to Market)
- Low Power Design, Analysis and Power Reduction Methodologies and Techniques, Static and Dynamic Low Power Verification
- Static and Formal Verification (Advanced Linting, Clock and Reset Domain Verification, Timing Exception Verification, Formal Property Verification, Formal Apps)
- Design and Verification Debug (RTL/Gates, Testbench, UVM, Protocol, UPF, Hardware/Software)
- Test Automation (Design-for-Test (DFT), Yield Analysis, ATPG, Diagnostics, Compression)
- Accelerating SoC Verification (Verification Planning & Coverage, Analog-Mixed Signal, UVM Verification)
- Functional Safety Verification (Fault Modeling, Fault Simulation)
- Applying Advanced Technologies (7/10/14/16nm, 3DIC, FinFET)
- Maximizing Results with Established Technology Nodes
- Accelerating Functional ECOs
- Characterization (Standard Cell, Memory, I/Os, Complex Cells)
- FPGA Design and Verification
- Prototyping (Virtual Prototyping, HAPS, Hybrid Prototyping)
- System Design and Validation
- Design Closure and IC Signoff (DRC/LVS, STA, Extraction)
- Full Custom Design and Methodologies
- IP Integration into SoCs (Interfaces, Processors, Security, Foundation IP, etc.)
- Addressing Software Quality and Security Concerns
- Managing and Optimizing the Compute Infrastructure for EDA Applications
Please carefully read the following notice before submitting your written materials to the SNUG program.
By submitting materials to the SNUG program, you and your employer are giving Synopsys the following rights: to reproduce, publish and distribute the submitted materials on the SNUG web site for access by Synopsys employees, contractors, and licensees.
It is your responsibility to confirm that your employer agrees to the use described above. You and your employer reserve the right to modify the submitted materials at any time. Synopsys shall reproduce any copyright or other legal notices that you include in your submitted materials. Synopsys will not use your submitted materials for product marketing purposes without first obtaining your express written consent.
If you have any questions about this copyright statement, please contact the SNUG team before submitting your proposal.
For the complete author submission timeline, please view the Author's Kit.
Want to know more? Review the SNUG Call for Papers FAQ
Have a question? Ask your SNUG Team
We look forward to hearing from you!
Your Innovation, Your Community