Call for Papers is now closed. Please contact your local AC or SNUG Team with any questions.
If you have used Synopsys technology to overcome difficult design issues and to accelerate your innovation, the SNUG community wants to hear from you!
Share your experience using Synopsys tools and IP at the 2016 Synopsys Users Group (SNUG), Germany. SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.
As a published SNUG author you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you’ll be eligible for significant cash awards.
The call for papers is open November 24, 2015 – February 4, 2016. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by February 5, 2016.
We have a preliminary list of topics to get you started. But, don’t let that limit your ideas or innovation in your submission.
- Advanced Application Methodologies s (CPU’s [ARM, MIPS, ARC], Graphics/GPUs, Other Processors)
- Advanced Design Methodologies (High Performance, Low Power, Area Optimization, Time to Market)
- Low Power Design, Analysis and Power Reduction Methodologies and Techniques
- Test Automation (Design-for-Test (DFT), Yield Analysis, ATPG, Diagnostics, Compression)
- Accelerating Verification (Verification Planning, Full Chip, Block, Coverage Closure, Analog-Mixed Signal, Verification IP (VIP), Dynamic and Static Low Power, CDC Checking, Mutation Analysis, Formal Analysis)
- Hardware/Software Debug and Visualization
- High Performance Emulation and Transaction Based Acceleration
- Applying Advanced Technologies (7/10/14/16nm, 3DIC, FinFET)
- Maximizing Results with Established Technology Nodes
- Accelerating Functional ECOs
- Characterization (Standard Cell, Memory, I/Os, Complex Cells)
- FPGA Design and Verification
- Prototyping (Virtual Prototyping, HAPS, Hybrid Prototyping)
- System Design and Validation
- Design Closure and IC Signoff (DRC/LVS, STA, Extraction)
- Full Custom Implementation, Verification and Methodologies
- Integrating IP into SoC Designs & Sub-systems
- Addressing Software Quality and Security Concerns
- Managing and Optimizing the Compute Infrastructure for EDA Applications
- Design for Automotive
Please carefully read the following notice before submitting your written materials to the SNUG program.
By submitting materials to the SNUG program you and your employer are giving Synopsys the following rights: to reproduce, publish and distribute the submitted materials on the SNUG web site for access by Synopsys employees, contractors, and licensees.
It is your responsibility to confirm that your employer agrees to the use described above. You and your employer reserve the right to modify the submitted materials at any time. Synopsys shall reproduce any copyright or other legal notices that you include in your submitted materials. Synopsys will not use your submitted materials for product marketing purposes without first obtaining your express written consent.
If you have any questions about this copyright statement, please contact the SNUG team before submitting your proposal.
For the complete author submission timeline, please view the Author's Kit.
If you have questions, please contact the SNUG Team