TSMC Awards 

 
2015 Interface IP Partner of the Year Award given to Synopsys during TSMC's OIP Forum
2015 Interface IP Partner of the Year Award given to Synopsys during TSMC's OIP Forum

Synopsys Selected as TSMC's 2015 "Interface IP Partner of the Year" for Sixth Consecutive Year

Synopsys was presented with TSMC's 2015 "Interface IP Partner of the Year" award at the TSMC Open Innovation Platform (OIP) forum held on September 17 at the Santa Clara Convention Center. Synopsys has been honored with this award every year since its inception in 2010. The award selection criteria includes customer feedback, TSMC9000 compliance, number of customer tape-outs and technical support excellence. Synopsys' portfolio of silicon-proven DesignWare Interface IP including USB, PCI Express®, DDR, MIPI, HDMI, SATA, Ethernet and Bluetooth Smart are available now in a wide range of TSMC process technologies including 16FF+.

   
Synopsys receives TSMC's Partner of the Year Award for Joint Development of 10-nm FinFET Design Infrastructure
Synopsys receives TSMC's Partner of the Year Award for Joint Development of 10-nm FinFET Design Infrastructure

TSMC Awards Synopsys "Partner of the Year 2015" for Joint Development of 10-nm FinFET Design Infrastructure

On September 17, during TSMC's Open Innovation Platform forum, TSMC awarded Synopsys "Partner of the Year 2015" for joint development of the 10n-nm FinFET design infrastructure. Synopsys' digital and custom design tools are broadly certified for 10-nanometer FinFET, including reference flows. Certified tools include: IC Compiler™ II for routing and placement, IC Validator DRC, LVS and metal fill, StarRC™ 10-nm multi-patterning and 3-D FinFET modeling, PrimeTime® signoff-accurate timing analysis, PrimeRail accurate static and dynamic IR-drop analysis, NanoTime static timing analysis of 10-nm embedded SRAMs, Galaxy Custom Designer® Schematic Editor, Laker® Layout for 10-nm, HSPICE®, CustomSim™ and FineSim® simulation products for 10-nm FinFET device modeling and accurate circuit simulation results for analog, logic and SRAM designs.