Achieving Optimum Results on High-Performance Processor Cores

This video was taken during Synopsys’ User Group (SNUG) in Silicon Valley on March 25, 2013, where attendees had the opportunity to hear from a panel of designers, with hands-on experience, share their insights and best practices for achieving optimum results on high-performance processor cores.
Brian Millar, ShiChin Ouyang, Frédéric NYER

Designing for GLOBALFOUNDRIES 20nm Technology and Beyond - Winning Through Collaboration
Designing for GLOBALFOUNDRIES 20nm Technology and Beyond - Winning Through Collaboration

Dr. Joerg Winkler is a Fellow at GLOBALFOUNDRIES in Dresden, Germany working within the Design Enablement group. On June 4, 2012, Synopsys hosted an IC Compiler luncheon during the Design Automation Conference (DAC) where Dr. Winkler spoke about designing at 20nm technology and beyond.
Dr. Joerg Winkler, Fellow, Design Enablement , GLOBALFOUNDRIES

GLOBALFOUNDRIES and Synopsys Discuss 20nm enablement

The 20nm process node poses a number of new, complex design tool challenges. Synopsys’ Andy Biddle asks GLOBALFOUNDRIES’ Richard Trihy how the company plans to enable its customers for this technology.
Richard Trihy, director Design Methodology,
Andy Biddle, product marketing manager, Synopsys

Innovation Optimized! Video

ARM, Common Platform and Synopsys executives share their views on the recent collaboration announcement to deliver a technology enablement solution for the design and manufacture of 32nm mobile devices.
Dr. Aart de Geus, Chairman of the Board and CEO, Synopsys; Michael Cadigan, General Manager, Microelectronics Division, IBM Systems and Technology Group; Dr. C.S. Choi, Executive Vice President, LSI Division, Samsung Electronics; Chia Song Hwee, President and CEO, Chartered Semiconductor Manufacturing ; Warren East, Chief Executive Office, ARM Holdings