GLOBALFOUNDRIES 

Creating Exceptional Solutions through True Collaboration 
GLOBALFOUNDRIES
Synopsys and GLOBALFOUNDRIES have a long history of collaboration dating back to 180-nm. Building on silicon-proven products including the Lynx Design System, Galaxy Implementation Platform and DesignWare IP (Figure 1), Synopsys and GLOBALFOUNDRIES are enabling our mutual customers to mitigate their project risks and streamline their implementation process to realize the highest quality first-time-right silicon success.

Synopsys' DesignWare® IP Supporting GLOBALFOUNDRIES Processes

The long-standing relationship between the two companies has resulted in the successful development of reference flows and DesignWare interface PHY, analog, logic libraries and embedded memory IP from 180-nm to 14-nm process technologies. Most recently this includes a Synopsys-based design “starter kit” for GLOBALFOUNRDRIES’ 14-nm FinFET technology, which provides designers with a built-in test case for out-of-the-box physical implementation testing and analysis of performance, power and area (PPA).

Synopsys' Optimized Design Environment
Figure 1: Synopsys' Optimized Design Environment

Synopsys' Silicon-Proven Optimized Design Environment for GLOBALFOUNDRIES 28-nm Process

Synopsys and GLOBALFOUNDRIES teamed up to deliver an optimized, pre-validated design environment for GLOBALFOUNDRIES 28-nm SLP high-k metal gate (HKMG) technology based on Synopsys' Lynx Design System. By leveraging the collaborative strengths of Synopsys and GLOBALFOUNDIRES, we are delivering a production-ready design solution based on the Galaxy Implementation Platform that enables our mutual customers to adopt the latest leading-edge technologies for their most advanced chips. Synopsys' support for the GLOBALFOUNDRIES HKMG 28-nm technology includes:

  • An optimized Lynx Design System
    • A design flow configured for the pre-validated ARM 28-nm SLP logic and embedded memory IP, that expedites design setup and start
    • GLOBALFOUNDRIES specific design methodology, guidelines and checks for the 28-nm SLP node that speed design closure and tape-out
    • A performance and power-optimized implementation flow for the ARM Cortex-A9 MPCore processor that targets GHz+ results using ARM physical IP
    • An environment for complete SoC integration of processors, peripherals and interface IP

28-nm and Below Leading-Edge Processes Driving New Technological Innovation

The emergence of critical new manufacturability issues at 28-nm and below leading-edge technologies continues to reinforce the need for earlier and even tighter ongoing collaboration between Synopsys and GLOBALFOUNDRIES. Key areas of collaboration include:

  • Faster yield ramp using Yield Explorer automated volume diagnostics to rapidly identify failure mechanisms and initiate process or design corrective actions
  • Silicon-proven implementation of Synopsys double-patterning aware 20-nm RTL2GDSII solution using the Galaxy Implementation Platform to ensure printability of device and interconnect layers in 20-nm IC manufacturing
  • Tapeout of GLOBALFOUNDRIES’ first complex 20-nm design using IC Compiler-Advanced Geometry (AG) and other components of Synopsys Galaxy Implementation Platform

14-nm FinFET Process is Next Major Step in Advanced Nodes

GLOBALFOUNDRIES 14-nm FinFET process is based on a technology platform that has already gained traction as the industry’s leading choice for high-volume, power-efficient system-on-chip (SoC) designs. To address the significant additional design demands for this highly advanced node, GLOBALFOUNDRIES and Synopsys have collaborated to develop a 14-nm FinFET RTL2GDS Reference Flow as part of GLOBALFOUNDRIES’ comprehensive digital design “starter kit” that also includes their technology-proven process design kit (PDK), early-access standard cell libraries, and a built-in test case for out-of-the-box physical implementation.

GLOBALFOUNDRIES’ digital design flows have been optimized to solve the challenges associated with the critical design rules of the 14nm technology node and includes newly introduced features such as implant-aware placement and double-patterning aware routing, In-Design DRC™ fixing and yield improvement, local/random variability aware timing, 3D FinFET extraction, and color-aware LVS/DRC sign-off.