System-Level Catalyst Member 

NoBug Logo With the growth of embedded software as a segment of chip design projects, traditional hardware verification is undergoing fundamental changes and improvements. The Synopsys System-Level Catalyst program enables NoBug to gain access to Synopsys system-level solutions in order to provide verification related services for the multimedia, telecommunications, networking and computer industries

- Moshe Shalev, CEO

Product Description
NoBug has been an early adopter of methodologies promoting reuse, interoperability and seamless integration of verification components.
NoBug VIPs have been implemented in either e or SystemVerilog, using recognized methodologies (eRM, VMM).
NoBug IPs provide for uniform handling of cross-environment concerns, promoting interoperability.

Our VIPs are ready-to-use, out-of-the-box verification environments, typically focusing on a specific protocol or architecture.
Each VIP comprises a complete set of elements for stimulating, checking, and collecting coverage information on the device under test (DUT) implementation of the VIP protocol or architecture. It expedites creation of a more efficient test bench for the DUT and can work with both Verilog and VHDL designs.

Finally, one can use a VIP as a full verification environment, or add it to an existing environment. There are several types of verification IPs that NoBug has developed; for details visit:

Interoperability Description and Customer Benefit:
NoBug is a SystemVerilog Verification IPs provider, and a member of the DesignWare® Verification IP (VIP) Alliance Program, whose VIPs integrate seamlessly with Synopsys' Virtual Prototyping tools. NoBug also provides services for system-level integration.

Tell me more about NoBug and DesignWare System-Level Library, Virtualizer and Virtual Prototyping.

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