20X Faster - Accelerated Power Analysis with Synopsys Verdi Technologies (Part 4 of 4)
In this webinar, discover how Verdi technologies – Siloti Correlation and Siloti What-If Replay Simulation enable early and accurate power estimation by using RTL simulation results to generate gate-level simulation data, without the need for gate-level environment bring up. This new Verdi Power Analysis Acceleration flow runs up to 20X faster and offers accuracy within 5%, compared to the traditional flow. Additionally, parallel run technology further enhances the speedup to up to 60X.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Chun Chan, R&D Director, Verification Group, Synopsys, Inc.
Nov 08, 2016

How Reliable is Your FPGA Design? Tips for Building-in High Reliability and Functional Safety
In this webinar, you will learn how to automatically “build-in” high reliability with Synopsys Synplify Premier FPGA design tools.
Paul Owens, Technical Marketing Manager, Synopsys, Inc.
Sep 27, 2016

ON Semiconductor and Synopsys: ISO 26262 and Automotive DFT Requirements
In this webinar, you will learn about the ISO 26262 functional safety standard and how it is driving DFT requirements today.
Chanthachith Souvanthong, Corporate Functional Safety Manager, ON Semiconductor; Adam Cron, Principle Engineer, Synopsys, Inc.; Steve Smith, Sr. Marketing Director, Synopsys, Inc.
Sep 22, 2016

Comprehensive Power Optimization Solution for Faster RTL Signoff (Part 3 of 4)
In this webinar, we will discuss how SpyGlass Power delivers an integrated early power analysis and exploration solution that includes: estimation, profiling, reduction and exploration.
Kiran Vittal, Product Marketing Director, Verification Group; Ken Mason, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Sep 21, 2016

Formal Debug: Achieving Faster Root Cause Analysis of Formal Results with VC Formal and Verdi
Based on years of hands-on experience and the latest debug features of VC Formal with Verdi, this webinar will give a practical guide to various debug techniques for analyzing formal verification results that will enable verification teams to get the most out of integrating formal verification into their flow. Using debug challenges such as assertion failures and sequential equivalence mismatches this webinar will guide users on the fastest way to a resolution. It will also show Navigator - a powerful new debug solution in Verdi – that allows quick waveform based what-if analysis on design functionality without any need for a testbench environment or assertion expertise.
Prapanna Tiwari, Senior Manager, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D. Formal Verification CAE Manager, Synopsys
Sep 14, 2016

Thinking ‘Outside the Waveform’ – Boosting Design Debug Productivity with Verdi
In this Synopsys webinar, we will show how you can cut your debug time in half with innovative Verdi design debug techniques. Specifically, you will learn how Verdi enables you to quickly explore, visualize and debug complex, and even unfamiliar designs; how you can quickly root-cause and debug simulation failures with Verdi debug techniques such as temporal flow view, automated X-tracing, assertion analyzer etc; and how Verdi’s unified debug platform extends the intuitive and familiar Verdi debug use-model to natively integrated Synopsys static and formal verification solutions.
Vaishnav Gorur, Product Marketing Manager, Verification Group, Synopsys; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys
Sep 13, 2016

New Use Cases and Advantages of MIPI Specifications in Mobile, Automotive and IoT SoCs
Learn about the key advantages of MIPI CSI-2 and DSI through application uses cases, as well as MIPI's new I3C specification and its advantages for multiple sensor connectivity.
Hezi Saar, Product Marketing Manager, Synopsys, Inc.
Sep 07, 2016

Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug (Part 2 of 4)
In this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent. Specifically, you will learn how visualization of the power architecture can help identify power strategy and connectivity issues upfront; how to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL; how to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Aug 31, 2016

Learn About SpyGlass CDC/RDC New Features (Japanese)
Learn about the latest new features for SpyGlass CDC/RDC including "Smart Netlist Verification" and "RDC (Reset Domain Crossing)".
Nobutaka Ogiya, Senior Application Engineer, NSGK, Synopsys, Inc.
Aug 30, 2016

Addressing Low Power Verification Challenges with Advanced Static Checking and Native Low Power Simulation (Part 1 of 4)
In this session, we will discuss UPF based static and dynamic verification techniques to address these challenges. We will also discuss the problems addressed by Synopsys’ VC LP and VCS NLP tools, to streamline the entire verification process.
Kiran Vittal, Product Marketing Director, Verification Group; Amol Herlekar, Sr. Staff Engineer, Verification Group, Ankush Bagotra, Staff Engineer, Verification Group, Synopsys, Inc.
Aug 10, 2016

Speed Software Development and IP Validation for ARMv8-based SoCs with Juno ARM Development Platform
This webinar introduces the new HAPS adaptor to connect a Juno ARM® Development Platform (ADP) to a Synopsys HAPS® Prototyping System or DesignWare® IP Prototyping Kit .
Achim Nohl, Technical Marketing Manager, Synopsys; Hugo Neto, Technical Marketing Manager, Synopsys
Jul 21, 2016

Time-travel in a SystemVerilog/UVM world – Interactive Testbench Debug Unleashed!
In this Synopsys webinar, we will show how interactive debug is ushering in a new era in testbench debug. Specifically, you will learn: how interactive and reverse interactive debug capabilities allow you to quickly root-cause and debug simulation failures; how what-if analysis improves TB debug efficiency by combining diagnosis and cure into a single step; how to navigate and effectively debug a UVM-based testbench
Vaishnav Gorur, Product Marketing Manager, Verification Group; and Mansour Amirfathi Sr. CAE Manager, Verification Group, Synopsys, Inc.
Jul 20, 2016

Successful SoC Implementation of USB Type-C and DisplayPort Alt Mode (Chinese)
This webinar discusses how to integrate USB Type-C and DisplayPort functionality, including solving critical hardware and software partitioning challenges.
Tom Liu, Field Application Engineer, Synopsys
Jul 19, 2016

Foundation IP for Automotive ICs: What Do You Need?
Learn what to look for when selecting Foundation IP for your automotive IC. Your PPA requirements are a given — learn about specific automotive requirements such as ISO 26262, TS 16949, zero DPPM & more
Prasad Saggurti, Senior Manager, Foundation IP Product Marketing, Synopsys
Jul 19, 2016

Selecting the Correct Mathematical Format to Achieve Design Precision
Learn about mathematical requirements for your targeted applications as well as new formats for use in hardware mathematics that can help you make clear design trade-offs and achieve design precision.
Kiran Kumar, Corporate Applications Engineer, Synopsys Inc.
Jul 14, 2016

Programmable Accelerators for Modern SoCs: When Hardware Accelerators Also Require Flexibility
Learn about the power of Application-Specific Instruction-Set Processors (ASIPs) and the growing need for more flexible, programmable accelerators for SoC designs.
Steve Cox, Sr. Manager, Business Development, Synopsys, Inc.
Jul 13, 2016

Test & Repair of SoCs for Functional Safety Applications (Chinese)
Learn about diagnosis, debug and self-test and repair solutions for memories, logic, AMS and interface IP blocks for automotive requirements to satisfy key criteria like low DPPM.
Qiuer Huang, STAR Memory System FAE, Synopsys
Jul 12, 2016

Securing IoT Systems with a Root of Trust (Chinese)
Security is critical to the success of IoT SoCs and must be an early design consideration. This webinar discusses IoT security threats and use cases requiring a secure root of trust.
Tom Liu, Field Application Engineer, Synopsys, Inc.
Jul 05, 2016

Enabling Machines to See with Efficient Embedded Vision Processors
Learn how Synopsys’ new embedded vision processor family with advanced vision capabilities can enable powerful and flexible vision solutions for your next-generations SoCs.
Michael Thompson,Sr. Product Marketing Manager for ARC and EV Processors, Synopsys, Inc.
Jun 29, 2016

Samsung and Synopsys 14nm Physical Verification in IC Validator and In-Design with IC Compiler II
Samsung and Synopsys together present a webinar on the manufacturing and physical verification challenges and solutions at 14nm.
KK, Lin, Director of Foundry Design, Samsung; Jonathan White, CAE Directory, Synopsys, Inc.
Jun 28, 2016

STMicroelectronics Sees Smarter, Faster Sign-off Cycles with Latest StarRC
STMicroelectronics will share their experiences with performance and efficiency advantages seen with the latest releases of StarRC and how they are helping ST to roll out their own products.
Raphael Gras, Sr. Digital Sign-off CAD Engineer, STMicroelectronics
Jun 23, 2016

Accelerate Development of Powertrain ECUs with Virtual Hardware
This 60-minute Webinar will provide an overview of virtual hardware ECUs and how to integrate them into the automotive system development process to manage these challenges.
Marc Serughetti, Business Development, Synopsys, Inc.
Jun 21, 2016

Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solution
This webinar will provide an overview of the concepts, requirements, and approaches for automotive IC designers and verification teams to understand what’s needed for ISO 26262 compliance for safety-critical SoCs and IP blocks. Capsule Module: Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solution
Brian Davenport, Staff Engineer, Synopsys’ Verification Group; David Hsu, Director of Product Marketing, Synopsys’ Verification Group
Jun 16, 2016

Double the Value - Accelerated SoC Verification AND Earlier Software Bring-up with Verdi HW SW Debug
In this webinar, we will show how simultaneous, synchronized views of design behavior at the software and hardware levels helps engineers at both levels debug efficiently and effectively. We’ll demonstrate how the Synopsys Verdi HW SW Debug solution seamlessly combines the industry-leading Verdi hardware debug with Eclipse-based software debug to provide a simple, yet powerful unified debug environment. Further, we will show how the solution is adapted easily to different processor core families including custom cores, as well as how it scales to debug multiple cores on a single SoC. Overall, these techniques will enable better SoC verification, accelerate software bring up and help achieve faster time-to-market.
Vaishnav Gorur, Product Marketing Manager, Synopsys, Inc. Alex Wakefield, Engineer, Synopsys, Inc.
Jun 15, 2016