Former Atrenta Products 

Synopsys Welcomes Atrenta 

Verification requirements have exploded as designs have become increasingly complex. Atrenta's early design analysis tools enable efficient, early verification and optimization of SoC designs at the RTL level. Combined with Synopsys' industry-leading verification technologies, Atrenta's leading static and formal technology further strengthens Synopsys' Verification Continuum™ platform and enables customers with this unique verification environment to meet the demands of today's complex electronic designs. Atrenta's SoC design analysis technology also fortifies the Synopsys Galaxy™ platform with additional power, test and timing-related analysis technologies. By integrating Atrenta's complementary technology into Synopsys' platforms, Synopsys can offer designers a more comprehensive, robust portfolio of silicon to software solutions for today's complex electronic systems.

  • Products
 

SpyGlass Lint
Early design analysis for logic designers


SpyGlass CDC
Closing the verification gap


SpyGlass DFT
RTL fault coverage analysis and design-for-test rule checking


SpyGlass Power
Complete solution for early Power optimization and verification


SpyGlass Constraints
Specify Constraints early, validate continuously and automate handoff


SpyGlass Physical
Early implementation readiness analysis for RTL blocks


GenSys RTL
Powerful & easy to use RTL restructuring


GenSys Assembly
Programmed chip assembly


 
Full-chip assertion synthesis product that leverages design and testbench information to automatically generate assertions and functional coverage properties