TCAD Application Advanced Example (3D) 

Process and Device Simulations of Trench Capacitor Embedded 70 nm DRAM  

Figure 1
Figure 1: A sequence of six snapshots during the 3D process simulation of a DRAM structure starting from silicon substrate with the shallow trench isolation (1) to the deep trench capacitor formation (2)-(4) and finally the access transistor formation (5) and (6). To exploit the symmetry of the structure, the 3D process simulation domain extends over just a quarter and is later extended to one half of the DRAM structure.

Figure 2
Figure 2: Final doping profile of a trench embedded DRAM single cell structure.

Overview
This application note showcases the TCAD Sentaurus 3D simulation capabilities for a trench capacitor embedded 3D DRAM cell.

DRAM process technology has been on the leading edge of semiconductor technology, with the density of DRAM quadrupling every three years. As the design rule of DRAM shrinks to sub-80nm, data retention time, cell-capacitance, and parasitic capacitance become the primary factors that determine device performance. At these shrinking dimensions, genuine 3D effects become more pronounced. The strong 3D capabilities of TCAD Sentaurus enable engineers to investigate 3D effects using simulations.

3D process simulation is performed using Sentaurus Process. For this 3D process simulation set-up, Sentaurus Process dispatches all geometrical operations such as etching and deposition internally to Sentaurus Structure Editor. The diffusion steps in Sentaurus Process are performed using the three-stream with charged point defects.

For an efficient evaluation of the most important electrical characteristics of the DRAM cell, this simulation project applies two different re-meshing strategies. For the evaluation of the off-state leakage current the region under the access transistor is well resolved, where as a separate simulation to determine the trench capacitance means the resolution is more focused on the surfaces in the capacitor.

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