In the last few years, the trend in CPU performance improvement has shifted from raw computational speed to parallelism as various memory and power (heat dissipation) limits have been reached at the higher clock frequencies. After surpassing clock speeds of 3 GHz, further CPU performance improvement is now achieved by increasing the number of computational elements (cores) within a given CPU package.
Steve Hollands, R&D Manager, Synopsys, Inc., George Mekhtarian, Product Marketing Manager, Synopsys, Inc.

In today’s complex system-on-chip (SoC) designs, static and dynamic voltage-drop and electromigration (EM) effects are increasing. At 90 nanometer (nm) and below, these effects are having a profound impact on timing, contributing 10 to 15 percent delay sensitivity and overall design viability. Due to the performance sensitivity to power and ground (P/G) noises, rail analysis solutions that have been used in high performance networking, wireless/mobile or low-power consumer applications become critical for all design applications at advanced process nodes.
Joy Han, Implementation Group, Synopsys

An accepted trend in the semiconductor industry, where process geometry is continuously shrinking, is the growing impact of variation in static timing analysis (STA). The growing impact of variation in modern designs requires an improved OCV handling capability that takes advantage of improved device-level variation techniques. This white paper highlights the Advanced OCV solution, a sophisticated technology from PrimeTime for providing the right balance between accuracy and performance.
Sunil Walia, Product Marketing Manager, Synopsys

Accurate parasitic extraction is critical to the success of high-performance integrated circuit (IC) design due to its impact on circuit timing, signal integrity and functionality. Synopsys’ StarRC™ Fast Field Solver (FFS) solution with Raphael NXT offers high-accuracy 3D capacitance extraction with full-chip performance and capacity for reference validation and signoff analysis. This paper presents the StarRC FFS solution and the benefits it provides to IP and IC designers.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager

Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The Synopsys StarRC™ extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level custom digital, analog/mixed-signal and memory designs.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager

Path-based analysis is a feature which was introduced in PrimeTime Y-2004.06 release. This technology offers a substantial improvement in static timing analysis accuracy for both PrimeTime and PrimeTime SI. This paper looks discusses this exciting technology, explores how it is implemented and discusses how to put it to work immediately in your PrimeTime or PrimeTime SI flow.
Chris Papademetrious, Corporate Applications Engineer, Synopsys Implementation Group

When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP.
Michael Robinson, Senior Design Consultant, Synopsys Professional Services

Fixing hold violations is normally a straightforward process of inserting a delay at a pin that has a negative hold slack. The challenge is choosing the amount of delay so that it improves or resolves the hold violation without incurring a setup violation. PrimeTime provides a capability called Distributed Multi-Scenario Analysis (DMSA). This capability provides a mechanism for running multiple full PrimeTime analyses while interfacing to them with a single PrimeTime control shell called the master.
Chris Papademetrious, Corporate Applications Engineer, Synopsys Implementation Group

Design closure in today’s advanced designs requires a delicate balance of many complex issues. Timing remains critical, but power has become important toward achieving design success. Today, power management is a mainstream design challenge and a key concern for chip designers.
Gordon Yip, Product Marketing Manager, Synopsys, Inc.

With the continued evolution of processes reaching levels below 90-nanometers (nm), nanometer effects are having a significant and growing impact on delay and require a number of changes in the approaches used to predict delays.
Dr. Larry G. Jones, Implementation Group, Synopsys, Inc.

The physical implementation of very deep sub-micron (VDSM) designs benefits from good, up-front planning processes, both in terms of schedule as well as quality of results. While the optimal planning strategy is design-dependent, there are a variety of design best practices that have proven successful in streamlining the physical design process.
Sachin Idgunji, Steve Lloyd, Rick Mitchell, Ron Spillman, Jon Young