| Mar 19, 2013 | Micronas Standardizes on Synopsys’ Design and Verification Solutions for Automotive Designs
Solutions Include Galaxy Custom and Digital Implementation, Discovery Verification Platform
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| Jan 22, 2013 | Synopsys Accelerates Adoption of FinFET Technology with Production-Proven Design Tools and IP
FinFET Technology Support Developed over Five-year Collaboration with Industry Leaders
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| Oct 15, 2012 | Synopsys and TSMC Collaborate for 20nm Reference Flow
Design Tools in Synopsys® Galaxy™ Implementation Platform selected in 20nm Reference Flow for Physical Implementation, RC Extraction, Timing Analysis and Physical Verification
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| Oct 11, 2012 | Synopsys and TSMC Deliver 3D-IC Design Support
Design Tools Selected in TSMC's First Integrated, Validated Reference Flow and Design Kit Enabling Multi-Die Integration Using TSMC CoWoS Technology
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| Jun 04, 2012 | Synopsys and Samsung Deliver a Complete Solution for 20-Nanometer Node
Solution Includes Place and Route, Physical Verification, and Signoff Design Tools
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| Feb 28, 2012 | BiTMICRO Selects Synopsys for Chip Design Automation
Two third-generation SSD controllers taped out using Synopsys' Galaxy Implementation and Discovery Verification Platforms
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| Feb 09, 2012 | CSR Selects Synopsys for Advanced-Node SoC Design
Adoption of Synopsys Galaxy Platform Driven by Superior Results for ARM CPU-based SoCs
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| Dec 14, 2011 | GUC Achieves Gigahertz+ Frequency on ARM Processor with Synopsys IC Compiler
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| Dec 14, 2011 | Synopsys Enables Silicon Success for GLOBALFOUNDRIES First Complex 20-nm Design
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| Oct 25, 2011 | eSilicon Selects Synopsys' Custom IC Design Solution and Tapes Out 28-nm Designs
Comprehensive Solution Enables Rapid Ramp-up and Delivery of Advanced Custom IP
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| Jul 11, 2011 | Synopsys and GLOBALFOUNDRIES Collaborate to Deliver 65nm iPDKs
Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Interoperable Process Design Kits (iPDKs)
Synopsys Custom Design Solution Now Supported by GLOBALFOUNDRIES 65nm Process Technologies
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| Jan 31, 2011 | Synopsys Galaxy Implementation Platform Addresses Gigascale Design
Latest Release Includes Scalability, Convergence and Throughput for Large IC Implementation on Advanced Node Technology
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| Aug 09, 2010 | Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process
Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities
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| Aug 05, 2010 | Synopsys Custom Design Tools Enable Creative Chips to Achieve First-pass Silicon Success
Unified Cell-Based and Custom Implementation Solution Key to Accelerating Time-to-Market
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| Jun 14, 2010 | Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories
Comprehensive Solution Delivers Golden Accuracy and Compact Libraries
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| Jun 14, 2010 | Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X
Rapid3D Technology Solves Sub-45nm Extraction Accuracy and Runtime Challenges for Custom IC Design
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| Jun 14, 2010 | PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances
HyperScale Technology Delivers 5 to 10X Boost in Performance and Capacity
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| Jan 11, 2010 | Synopsys Speeds Timing Signoff by 2X With Latest Multicore Technology
PrimeTime 2009.12 Delivers New Threaded Multicore Performance to Address Signoff Bottleneck
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| Sep 21, 2009 | Synopsys Unveils StarRC Custom Parasitic Extraction Solution
Expands Custom Design Portfolio with Unified Extraction Solution
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| Jul 24, 2009 | Synopsys Introduces Galaxy Constraint Analyzer to Improve Designer Productivity
Speeds RTL-to-GDSII Turnaround Time Through Look-ahead Constraint Analysis
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| Jul 20, 2009 | Synopsys Introduces IC Compiler In-Design Rail Analysis to Accelerate Design Closure
Synopsys, Inc., today introduced its In-Design Rail Analysis™ capability to accelerate design closure. Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.
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| Jun 09, 2009 | TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow
Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that TSMC selected Synopsys' Galaxy™ Implementation Platform for their new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler® synthesis and IC Compiler physical implementation solutions, and the PrimeTime® sign-off and Star-RCXT™ extraction solutions - the industry yardsticks for IC design sign-off. The new flow is now available for 65-nanometer (nm) designs with planned extensions into other process technology nodes.
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| May 14, 2009 | Synopsys PrimeTime PX Power Analysis Solution Achieves Broad Market Adoption
Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that Synopsys’ PrimeTime® PX solution, a key component of the Galaxy™ Implementation Platform and part of Synopsys’ Eclypse™ low power solution, has been successfully deployed at more than 175 semiconductor companies worldwide to perform highly accurate dynamic and leakage power analysis. Seamless integration within PrimeTime, the golden industry standard for timing and signal integrity signoff, has resulted in the selection of PrimeTime PX as the preferred power analysis solution at companies from all facets of the semiconductor industry.
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| May 13, 2009 | MediaTek Adopts Synopsys PrimeTime SI for Timing and Signal Integrity Signoff
Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multi-media solutions, has adopted Synopsys’ PrimeTime® SI solution for static timing analysis (STA) and signal integrity (SI) signoff. MediaTek selected the Synopsys PrimeTime SI solution to streamline the signoff flow for its new cutting-edge system-on-chip (SoC) designs targeted at 65-nanometer (nm) and below process technologies.
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