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Apr 14, 2014TSMC Certifies Synopsys Digital and Custom Solution for V1.0 N16 Process
Certification Enables Designers to Realize the Power, Performance and Area Benefits of FinFET Technology

Mar 24, 2014Synopsys Unveils IC Compiler II, Enabling a Game-Changing, 10X Increase in Physical Design Throughput


Sep 23, 2013Synopsys Implementation Solution Included in TSMC 16-nm Reference Flow for FinFET Design


Mar 19, 2013Micronas Standardizes on Synopsys’ Design and Verification Solutions for Automotive Designs
Solutions Include Galaxy Custom and Digital Implementation, Discovery Verification Platform

Jan 22, 2013Synopsys Accelerates Adoption of FinFET Technology with Production-Proven Design Tools and IP
FinFET Technology Support Developed over Five-year Collaboration with Industry Leaders

Oct 15, 2012Synopsys and TSMC Collaborate for 20nm Reference Flow
Design Tools in Synopsys® Galaxy™ Implementation Platform selected in 20nm Reference Flow for Physical Implementation, RC Extraction, Timing Analysis and Physical Verification

Oct 11, 2012Synopsys and TSMC Deliver 3D-IC Design Support
Design Tools Selected in TSMC's First Integrated, Validated Reference Flow and Design Kit Enabling Multi-Die Integration Using TSMC CoWoS Technology

Jun 04, 2012Synopsys and Samsung Deliver a Complete Solution for 20-Nanometer Node
Solution Includes Place and Route, Physical Verification, and Signoff Design Tools

Feb 28, 2012BiTMICRO Selects Synopsys for Chip Design Automation
Two third-generation SSD controllers taped out using Synopsys' Galaxy Implementation and Discovery Verification Platforms

Feb 09, 2012CSR Selects Synopsys for Advanced-Node SoC Design
Adoption of Synopsys Galaxy Platform Driven by Superior Results for ARM CPU-based SoCs

Dec 14, 2011GUC Achieves Gigahertz+ Frequency on ARM Processor with Synopsys IC Compiler


Dec 14, 2011Synopsys Enables Silicon Success for GLOBALFOUNDRIES First Complex 20-nm Design


Oct 25, 2011eSilicon Selects Synopsys' Custom IC Design Solution and Tapes Out 28-nm Designs
Comprehensive Solution Enables Rapid Ramp-up and Delivery of Advanced Custom IP

Jul 11, 2011Synopsys and GLOBALFOUNDRIES Collaborate to Deliver 65nm iPDKs
Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Interoperable Process Design Kits (iPDKs) Synopsys Custom Design Solution Now Supported by GLOBALFOUNDRIES 65nm Process Technologies

Jan 31, 2011Synopsys Galaxy Implementation Platform Addresses Gigascale Design
Latest Release Includes Scalability, Convergence and Throughput for Large IC Implementation on Advanced Node Technology

Aug 09, 2010Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process
Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities

Aug 05, 2010Synopsys Custom Design Tools Enable Creative Chips to Achieve First-pass Silicon Success
Unified Cell-Based and Custom Implementation Solution Key to Accelerating Time-to-Market

Jun 14, 2010Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories
Comprehensive Solution Delivers Golden Accuracy and Compact Libraries

Jun 14, 2010Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X
Rapid3D Technology Solves Sub-45nm Extraction Accuracy and Runtime Challenges for Custom IC Design

Jun 14, 2010PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances
HyperScale Technology Delivers 5 to 10X Boost in Performance and Capacity

Jan 11, 2010Synopsys Speeds Timing Signoff by 2X With Latest Multicore Technology
PrimeTime 2009.12 Delivers New Threaded Multicore Performance to Address Signoff Bottleneck

Sep 21, 2009Synopsys Unveils StarRC Custom Parasitic Extraction Solution
Expands Custom Design Portfolio with Unified Extraction Solution

Jul 24, 2009Synopsys Introduces Galaxy Constraint Analyzer to Improve Designer Productivity
Speeds RTL-to-GDSII Turnaround Time Through Look-ahead Constraint Analysis

Jul 20, 2009Synopsys Introduces IC Compiler In-Design Rail Analysis to Accelerate Design Closure
Synopsys, Inc., today introduced its In-Design Rail Analysis™ capability to accelerate design closure. Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.




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