TSMC and Synopsys: 10nm Physical Verification Enablement for IC Validator
Learn about TSMC’s 10nm design enablement readiness & the tooling supported in their physical design flow; Synopsys will cover new technologies addressing the challenges of 10nm design verification.
Captain Liu, Manager, Design Methodology and Service Marketing TSMC; Ron Duncan, Sr. CAE Manager, Synopsys
Mar 03, 2016
Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
See the latest innovations in PrimeRail's In-Design solution including rail integrity and static/dynamic analysis that enable designers to achieve significant productivity in advanced node designs.
Jason Binney, Principle CAE, Synopsys
May 14, 2014