Moving From In-Design to Signoff with IC Validator

During SNUG 2012, industry experts at leading Japanese, European, and U.S. semiconductor companies discussed how success with In-Design physical verification is moving them towards IC Validator for signoff. This video captures the speakers presenting their experiences with new verification methodologies based on tight-loop integration with physical implementation and their discussion about how this approach has moved them towards IC Validator for final physical signoff with significant productivity gains.
Synopsys. Inc.

DAC 2010 IC Compiler In-Design Videolog

At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics

IC Validator for In-Design Physical Verification

IC Validator is a full, sign-off quality verification tool that delivers the highest performance to enable significantly improved time-to-tapeout with better DFM closure.
Antun Domic, senior vice president and general manager of Synopsys' Implementation Group