|Advanced Mixed-Signal Design and Verification of Smartcar ICs|
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014
|Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation|
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014
|Accelerating Time to a Quality Floorplan: Cisco Systems and Synopsys Share Their Insights|
Learn how IC Compiler’s new Data Flow Analysis (DFA) technology enables designers to accelerate time to a quality floorplan. Cisco Systems shares their experiences deploying this technology on a 100+ million gate ASIC to reduce floorplanning iterations with ASIC vendors and quickly identify and validate macro placement for the best quality of results.
Krishna Kumar Gundavarapu, Technical Leader, Cisco; Steve Kister, Technical Marketing Manager, Synopsys
Apr 23, 2014
|Enabling High-Frequency Clock Design: Imagination Technologies and Synopsys Share Their Perspectives|
Imagination Technologies discusses their high frequency design requirements and clock design strategies and Synopsys presents clock implementation technologies available in IC Compiler that boost performance, including the new concurrent clock and data optimization capability.
Stuart Vernon, Director of Physical Design, Imagination Technologies Limited; Sumit Roy, Group Director of R&D, IC Compiler, Synopsys
Oct 24, 2013
|Samsung Foundry and Synopsys Discuss Enabling 14-nm FinFET Design|
Samsung Foundry and Synopsys present the challenges and opportunities of manufacturing with Samsung's 14-nm FinFET process and how these changes impact design enablement.
Dr. Kuang-Kuo Lin, Director, Foundry Design Enablement, Samsung Semiconductor Inc. (SSI); Dr. Henry Sheng, Senior Director of R&D, Synopsys
May 28, 2013
|Recover Leakage and Maintain Signoff Timing – with Customer Case Studies|
This webinar will introduce PrimeTime ECO technology designed to recover leakage power, without introducing timing violations. We’ll share customer data that shows leakage power recovery up to 40%.
Rupesh Nayak, R&D Manager, Synopsys; Sasan Absalan, Corporate Applications Engineer, Synopsys
Jan 29, 2013
|Samsung and Synopsys Share Multicorner-Multimode Perspectives|
This webinar highlights strategies for dealing with the large number of scenarios in the physical implementation flow. Samsung Semiconductor Inc. shares their experience using the IC Compiler- based MCMM solution to successfully meet their aggressive design objectives and Synopsys shares its multicorner-multimode (MCMM) design solution for addressing variability and design complexity at advanced technology nodes.
Santhosh Pillai, Senior Engineering Manager, Samsung, San Jose (SSI); Thomas Andersen, Director of R&D, IC Compiler, Synopsys
Oct 31, 2012
|Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design|
Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys; Randy Bishop, Principal Engineer, Synopsys
Oct 24, 2012
|Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure|
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012
|Save Weeks Fixing ECOs with PrimeTime and IC Compiler|
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011
|Faster ECO Fixing Flows with PrimeTime and IC Compiler|
This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010