White Papers
Conference Papers
SNUG San Jose 2008
Randomized Testbench Development, a Case Study in USB
Jason Remple, Broadcom
Denis Bussaglia, Synopsys Professional Services
Frederic Krampac, Synopsys Professional Services
Radiation Hardened Electronics Technology (RHET) 2007
Designing Advanced ASIC’s with Synopsys Design Tool Suite
Rick Hayden, Synopsys Professional Services
SNUG Boston 2007
Hold Me Please! How to Fix Post-Route Hold Violations Quickly and Easily Using Distributed Multi-Scenario Analysis
Dwight Galbi, Analog Devices, Inc.
Beth Herman, Synopsys Professional Services
Brandon Waldo, Synopsys Professional Services
Mike Castellano, Synopsys Professional Services
Christopher Papdemetrious, Synopsys, Inc.
Advanced Low Power, Multi-Supply Implementation Techniques for 65nm and Beyond using DCT and ICC
Dwight Galbi, Analog Devices, Inc.
Brandon Waldo, Synopsys Professional Services
Finding A Tricky IP Bug with SystemVerilog Assertions (A Real World Example)
David E. Castle, Synopsys Professional Services
Paul McGaugh, Broad Reach Engineering, Inc.
IR-drop analysis of a UDSM complex power-gating design
Kaijian Shi, Synopsys Professional Services
Julio C. Hernandez, Synopsys Professional Services
Michael Allen, Analog Devices, Inc.
Dwight Galbi, Analog Devices, Inc.
Joe Geisler, Analog Devices, Inc.
Multiphase Flow for Meeting Metal Density and Gradient Requirements at 65nm
Jim Dodrill, Analog Devices Inc.
Dwight Galbi, Analog Devices Inc.
Moheb Basta, Synopsys Professional Services
Mike Castellano, Synopsys Professional Services
IEEE SoC 2007
A Wakeup Rush Current and Charge-up Time Analysis Method for Programmable Power Gating Designs
Kaijin Shi, Synopsys Professional Services
Jingsong Li, Synopsys, Inc.
SNUG San Jose 2007
Physical Design and Timing Challenges of a Serial PHY
Ken Umino, Synopsys Professional Services
Steve Everley, Everley Consulting
Ross Segelken, Synopsys
Jason Upton, Synopsys
John Stonick, Synopsys
Advantages of Driving DDR Interface Logic at 2x the DDR Clock versus 1x the DDR Clock
Ken Umino, Synopsys Professional Services
Pete Thoeming, Thomson Silicon Components
Applying CRV to Microprocessor Verification
Jason Chen, Synopsys Professional Services
Core Based Test using Scan Compression and Core Isolation
Sandeep Kaushik, Synopsys Professional Services
Paul Policke, Qualcomm
Decoupling Capacitance Estimation, Implementation and Verification: A Practical Approach for Deep Submicron SoCs
David Stringfellow, Synopsys Professional Services
John Pedicone, Synopsys Professional Services
DesignCon 2007
Power Network Synthesis of Power Gating Designs
Kaijian Shi, Synopsys Professional Services
Zhian Lin, Synopsys
Yi-Min Jiang, Synopsys
Comparison of a 1x Clock DDR Design Versus a 2x Clock DDR Design
Ken Umino, Synopsys Professional Services
Peter Thoeming, Thomson Silicon Components
GSPx 2006
Physical Design Techniques of a Multi-Protocol Serdes Phy
Ken Umino, Synopsys Professional Services
Jason Upton, Synopsys
Ross Segelken, Synopsys
John Stonick, Synopsys
SNUG Boston 2006
Methodology to Analyze and Insert a Power Mesh Early in Design Cycle
Joseph Schrand, Thomson Silicon Components
Ken Umino, Synopsys Professional Services
Evan Chen, Synopsys Professional Services
Technique for Optimizing IBM Power PC 440 Cache
David E. Castle, Synopsys Professional Services
Vijay Gullipalli, Synopsys Professional Services
Paul McGaugh, Broad Reach Engineering, Inc.
Taming the "Congestion" Beast – Methods to Handle Congestion during Physical Design Implementation
Lavanya Murugesan , Synopsys Professional Services
Nghi Huynh, Qualcomm, Inc.
Automated Response Generation for IP Based Subsystem Verification
Tony Ezell, Synopsys Professional Services
DAC 2006
Challenges in Sleep Transistor Design and Implementation in Low-Power Designs
Kaijian Shi, Synopsys Professional Services,
David Howard, ARM Ltd.
The 2006 World Congress in Computer Science
PSeuDoFFIL: Power Saving Datapath FiFo Insertion Logic
Josefina Hobbs, Synopsys Worldwide Application Services,
John McCardle, ATI,
John Lofgren, Synopsys Solutions Group
SNUG Europe 2006
Library Gotchas Guidelines to Physical Library Qualification
Lavanya Murugesan, Synopsys, Inc.,
Tamiko Yoneyama, Synopsys, Inc.,
Koshi Matsushita, Synopsys, Inc.
An efficient script-based RTL-to-GDSII flow using the Jupiter-XT - PC - Astro tool chain in 130 nm on a 350K-instance design
Pierre-Marie Signe, Abilis Systems
John Lofgren, Synopsys Professional Services, Synopys Inc.
SPIRIT-based IP Assembly and SDC promotion for a 65nm System-on-Chip using coreAssembler
Sal Tiralongo, Synopsys Professional Services, Synopys Inc.
Stephane Maulet, Synopsys Professional Services, Synopys Inc.
Emanuele Irrera, Synopsys Professional Services, Synopys Inc.
Olivier Florent, STMicroelectronics Ltd.
Philip Cuney, STMicroelectronics Ltd.
Cyril Vartanian, STMicroelectronics Ltd.
Rectilinear Supply Mesh Insertion using JupiterXT Virtual Flat Flow
Abid M. Jindani, Synopsys Professional Services, Synopys Inc.
Stephanie Miller, ARM Inc.
IEEE VLSI-DAT Taiwan 2006
Sleep Transistor Design and Implementation – Simple Concepts Yet Challenges To Be Optimum
Kaijian Shi, Synopsys, Inc.
David Howard ARM, Ltd.
Power-On Current Control In Sleep Transistor Implementations
Kaijian Shi, Synopsys, Inc.
David Howard ARM, Ltd.
SNUG San Jose 2006
Integrating System Models into an RVM Environment
Anand Acharya, Qualcomm
Shaun Evans, Synopsys Professional Services
1.2 – 1.5 + M instances flat design for 0.13um process
Steve Doan, Synopsys Inc.
Koshi Matsushita, Synopsys Inc.
Chien-yeh Wu, Synopsys Inc.
Srini Burugu, Synopsys Inc.
Automated FFT RTL creation using Verilog with Matlab and Perl
Richard Hayden , Synopsys Professional Services
Cole O’Berry, Synopsys Professional Services
John Kuhns , Synopsys Professional Services
DesignCon 2006
Back-End Methodology and Techniques for a Multi-Protocol Mixed Signal IP Design
Ken Umino, Synopsys Inc. Professional Services
Jason Upton, Synopsys Inc. Solutions Group
John Stonick, Synopsys Inc. Solutions Group
Ross Segelken, Synopsys Inc. Solutions Group
Bill Beale, Synopsys Inc. Solutions Group
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