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Conference Papers and Presentations
GSPx 2004
OCP/STBUS Plug-In Methodology
Giovanni Strano, Carlo Pistritto, STMicroelectronics
Salvatore Tiralongo, Synopsys Professional Services
Euro DesignCon 2004
Low Power Design Optimization Methodologies and Flows For Dynamic Power Reduction in 130nm and below ASIC technologies
James Shiffer, Artisan Components, Inc.
Jason Binney and Kaijian Shi, Synopsys Professional Services
Euro DesignCon 2004
Design Optimization Methodologies for Low-Leakage Power Designs in Sub-90nm
Technology
Kaijian Shi, Synopsys, Inc.
Jason Binney, Synopsys, Inc.
Boston 2004
Application of RVM for Vera On a Networking Design Case Study
Cristian Samoila, CIENA Inc
Jason C. Chen, Synopsys Professional Services
Boston 2004
Creating a SoC-Level Checker without Breaking a Sweat
Fraya H. Cohen, Synopsys Professional Services
Chi Duong, Freescale Semiconductor, Inc.
ESNUG 2004
Maximizing Vera Randomization in an Embedded Software Environment
Joachim Geishauser, Motorola
Anthony Ezell, Synopsys Professional Services
SNUG Europe 2004
Improving Design QoR with transition from DCPC-Astro to PC-Astro Flow (abstract)
Juha Liias, Synopsys Professional Services
SNUG Europe 2004
Integration and Verification of AMBA based IP (abstract)
Chris LeBlanc, Jeff Alderson, Synopsys Professional Services
SNUG Europe 2004
Implementation strategies of a large Xilinx Virtex II Pro Device (abstract)
Jeff Alderson, Synopsys Professional Services
SoC Conference 2004, Sweden
Practical Aspects of Using 3rd Party Semiconductor IP in SoC Design (abstract)
Jyrki Hyrsylä, Juha Peltoniemi and Pekka Leinonen, Synopsys Professional Services
DesignCon 2004
A New Design Optimization Approach to Multi-Million Gate ASIC
Thi Nguyen, Kaijian Shi, Synopsys, Inc.
SNUG San Jose 2004
Zero Defects. Verifying a complex PAD Ring using Open Vera Assertions
Laucresha Salmon, Motorola, Inc.
Hemendra Talesara, Synopsys, Inc.
DesignCon 2004
Effective Verilog RTL coding: Guidelines for "Coding for Coverage"
Hani Saleh, Peter Gillen, Synopsys Inc.
Archive
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