Featured Technical paper
Power Network Synthesis of Power Gating DesignsKaijin Shi, Synopsys Professional Services Zhian Lin, Synopsys, Inc. Yi-Min Jiang, Synopsys, Inc.

Figure 1: A recent Synopsys survey of industry designers indicated power challenges throughout the design flow, especially in power planning and analysis, dynamic and leakage power reduction and gate-level power analysis.

Synopsys Professional Services has a unique combination of power methodology expertise throughout the design flow and design experience in System-on-Chip (SoC) power optimization that will enable you to meet your power budget and ensure a predictable chip-level power signoff. Leveraging the Eclypse™ Low Power Solution , our consultants will not only help you achieve tape-out success for your current project, but also transfer knowledge and proven methodologies to address power issues in your future projects. Typical areas of power optimization consulting include:

• Dynamic power optimization. While RTL clock gating is a mature practice for reducing dynamic power, increasing design complexity with multiple clock domains and the resulting clock-tree design can be very challenging to integrate in the physical design. Synopsys consultants are experienced in deploying methodologies to reduce full-chip dynamic power using module-level, multi-stage, and hierarchical clock gating, gate-level power optimization and integrating the gated clock-tree in the physical design to ensure DFT, formal and sign-off compliant design.

• Leakage power optimization. At 90nm process technologies and below, up to half of the power dissipated by transistors can be due to leakage current. To minimize this static power consumption, Synopsys’ consultants apply a power-aware design flow that optimizes the use of multi-threshold (multi-Vth) voltage cells from RTL synthesis to post-route optimization and ensure timing closure is achieved within power budgets. Our consultants have authored leading publications on power network synthesis methodologies for reduced leakage; techniques include power gating (e.g. MTCMOS) and sleep transistor design, placement, and optimization.

• Multi-voltage design and integration. Varying voltages and dividing the chip into separately controlled voltage islands can provide significant power and energy savings, but this requires critical methodology changes throughout the entire design cycle, from architecture evaluation to RTL partitioning to full-chip signoff. Synopsys Professional Services can optimize your design flow to take advantage of the multi-voltage capabilities of the Synopsys Galaxy Design platform and help implement your multi-voltage SoC. Our consultants are also experienced in optimizing and integrating ARM® Intelligent Energy Management (IEM)-enabled SoCs.

• Power planning and analysis. Due to increased routing complexity and growing reliability concerns in today’s complex SoCs, design teams must accurately estimate chip power consumption and design the power grid accordingly. Otherwise, the power grid may have significant IR-drop issues that negatively impact device functionality and performance. Synopsys Professional Services employs advanced methods such as IR-drop driven power network synthesis to create an optimal, robust power grid to improve tape-out predictability.

• Chip rail analysis and signoff. The impact of power on final chip reliability necessitates thorough rail analysis and power network verification. Synopsys consultants use a proven signoff flow that analyzes the impact of IR-drop on performance, signal integrity, and test. With increasing challenges surrounding leakage current and the application of multi-voltage and power gating (also referred to as course-grain MTCMOS) our consultants can help mitigate the impact of “in-rush” current on long term reliability, signal integrity, and performance.

• DesignCon 2007
  Power Network Synthesis of Power Gating Designs
  Kaijian Shi, Synopsys Professional Services
  Zhian Lin, Synopsys
  Yi-Min Jiang, Synopsys
• SNUG San Jose 2007
  Decoupling Capacitance Estimation, Implementation and Verification: A Practical Approach for Deep Submicron SoCs
  David Stringfellow Synopsys Professional Services
  John Pedicone Synopsys Professional Services
  Core Based Test using Scan Compression and Core Isolation
  Sandeep Kaushik, Synopsys Professional Services
  Paul Policke, Staff Engineer Qualcomm, Inc.
  
• SNUG Boston 2006
  Methodology to Analyze and Insert a Power Mesh Early in Design Cycle
  Joseph Schrand, Thomson Silicon Components
  Ken Umino, Synopsys Professional Services
  Evan Chen, Synopsys Professional Services
• SNUG Europe 2006
  Rectilinear Supply Mesh Insertion using JupiterXT Virtual Flat Flow
  Abid M. Jindani, Synopsys Professional Services, Synopys Inc.
  Stephanie Miller, ARM Inc.
• The 2006 World Congress in Computer Science
  PSeuDoFFIL: Power Saving Datapath FiFo Insertion Logic
  Josefina Hobbs, Synopsys Worldwide Application Services
  John McCardle, ATI
  John Lofgren, Synopsys Solutions Group
• IEEE VLSI-DAT Taiwan 2006
  Power-On Current Control In Sleep Transistor Implementations
  Kaijian Shi, Synopsys, Inc.
  David Howard ARM, Ltd.
• Electronic Design
  Rail-Signoff Analysis Ensures SoC Power Integrity
  January 2006
• White Papers:
  Addressing Power Integrity Challenges for SoCs
  David Stringfellow, Staff Design Consultant, Synopsys Professional Services
  Kevin Knapp, Senior Design Consultant, Synopsys Professional Services
  A Practical Methodology for Calculating IR Drop Targets for Advanced Designs
  Michael Solka, Director of Physical Design Methodology, Synopsys Professional Services
  Jonathan Young, Director of Physical Design, Synopsys Professional Services
  Power Management In Complex SoC Design
  Jim Flynn, Synopsys Professional Services
  Brandon Waldo, Synopsys Professional Services