Pilot Design Environment A Ready-to-Use Production Proven Design System

Overview
Today’s nanometer process geometries and aggressive design schedules put tremendous pressure on design organizations, who must contend with the dual needs of completing their immediate projects on schedule in parallel with advancing their design infrastructure for the latest design challenges and process generations. While technical issues such as power management, timing closure, functional verification, and manufacturability continue to be key issues for design teams, project related challenges also present obstacles to productivity and predictability. For example, multi-site development, the quality and completeness of incoming IP, libraries, and tech files, and keeping the design flow and methodologies updated — all contribute to common project bottlenecks and overhead costs — your bottom line profit.

The Synopsys Pilot Design Environment is a comprehensive, production-ready design system that helps address both designrelated and project-related challenges while ensuring the latest updates in Very Deep Submicron (VDSM) design methodologies and best-practices.

Complete RTL-to-GDSII Design Environment

• Production-ready design flow based on Synopsys’ Galaxy™ Design and Discovery™ Verification Platforms
• BuiBuilt-in utilities for incoming IP and libraries QA, technology file preparation, and flow metrics monitoring
• Open and consistent data structure
• Flexible, reusable flow automation
• Intuitive GUI for project setup and flow configuration
• Deployed as a service to address customers’ specific design and tool needs

Figure 1: Pilot design environment overview.

Fast Track to the Latest VDSM Methodologies and Design Team Productivity
The Pilot Design Environment is a complete design system that can be quickly adopted by project teams — so they can focus on what they do best... IC design. The Pilot deployment service offering includes:

• TCL- and Perl-based scripts packages for a complete RTL-to-GDSII design flow, licensed as source code
  to provide maximum user flexibility. Pilot’s fully configurable design flow includes:
• A complete RTL-to-GDSII implementation flow based on Synopsys’ Galaxy tools and tapeout proven advanced methodologies supporting RTL synthesis through chip finishing and sign-off
• A complete functional verification flow based on Synopsys’ Discovery tools and Reference Verification Methodology (RVM) supporting RTL simulation through full chip regression
• Support for 3rd-party and in-house tool integration
• Built-in methodologies for qualification assessment (QA) of design inputs to identify and address common issues with incoming IP (i.e., RTL, netlist) and libraries early in the design cycle
• A Perl-based technology preparation utility to create a clean and complete set of control files for layout, extraction and physical verification steps
• A database that captures approximately fifty (50) design- and resource-related metrics throughout the flow, enabling real-time assessment of project bottlenecks and a consistent set of measurements for systematic improvements
• A GUI for new project setup, design specific flow configuration and Makefile generation
• Makefile-based automation with built-in error checking, providing robust designer-level control and visibility of flow execution
• An open, formal data structure that provides consistent organization of technology and design-related data
  to facilitate multi-user, multi-site chip development
• Support for popular commercial and free-ware revision control software
• Configuration of the environment for customers’ project-specific needs
• User training
• Sample design, reference guide and user documentation

Figure 2: Pilot incorporates a complete, 65nm-proven design flow.

Advanced, Tapeout-Proven Flows
The Pilot Design Environment includes a leading-edge design flow that is silicon proven on dozens of designs
in a wide range of applications and manufacturing processes, from 0.25 to 65nm. The hierarchical RTL-to-GDSII implementation flow consists of five (5) modular and configurable steps for synthesis, designfor- test, design planning, place and route, and chip finishing. It includes built-in support for concurrent modeling, analysis, and sign-off throughout the flow including static timing analysis (STA), formal verification, automatic test pattern generation (ATPG), power, rail and EM/IR analyses. The design flow also includes advanced design
methodologies to optimize for timing, signal integrity, test coverage, manufacturability and power management.

Keeping Your Environment Leading-Edge
Maintained and utilized by Synopsys Professional Services in its own IC design centers, the Pilot Design Environment undergoes continuous enhancements. A separate support contract for Pilot provides customers
CAE support and access to periodic updates to the design environment, ensuring customers can take advantage
of new features, methodologies and tool support in future Pilot releases.

“Our CAD team was able to deploy the Pilot Design Environment to a new site and start running the main flow steps almost immediately. Methodologies associated with designing advanced chips that take years to learn and understand were incorporated
into Pilot.”

— Benny Chang     
VP of Engineering, Tundra