Enabling the delivery of Super10 Nexus On-Chip-Emulator as a Soft IP

Abstract
Until today, hard IP was generally preferred in the IP market, mainly due to more predictive results and to an easier validation task. But the main drawback of hard IP is the lack of flexibility (in terms of specification, technological process and form factor). As a consequence, we observe an increasing need for soft IP. The challenge is to define soft IP with an associated implementation flow that enables to use soft IP, and its flexibility, with predictability similar to hard IP.

As an example of this evolution, "ST Microelectronics TPA/DSP&Micro Division" has decided to deliver its Super10 Nexus On-Chip Emulator as a soft IP, instead of as a hard IP, to increase the flexibility offered to its customers. A project jointly managed by ST Microelectronics and Synopsys Professional Services aims at packaging and delivering Super10 Nexus-OCE as a soft IP, using a methodology that should be disseminated inside ST Microelectronics.

By using the Synopsys' coreTools, and the corresponding methodology defined in a long-term cooperation between STM and Synopsys, a new version of the Super10 Nexus-OCE has been developed and can now be delivered as a coreKit. The used methodology will be presented in details in the current paper.

The Super10 Nexus-OCE cell provides facilities to the debugger in order to assist in application program debug. It is based on IEEE 5001 Standard (previously named NEXUS), and is supported by several debugging tool vendors. It is a companion cell of the Super10 microcontroller and is intended to be embedded on the final customer's chip. Super10 Nexus-OCE is now available as a coreKit, and in the near future the Super10 microcontroller cell itself will be delivered as a coreKit, then offering the two IPs within the same environment.

The packaging work consist mainly in defining configuration parameters of the cells, implementing them in the RTL source code, preparing the implementation flow required for integrating the IP inside a final chip, and validating it in a real design using the coreKit. Thanks to coreBuilder, scripts for synthesis, simulation, timing analysis, fault coverage, and formal equivalence are prepared and included in the coreKit as a deliverable of the soft IP.

The result is a configurable IP, offering large configuration features to the customers, associated with a secure and proven implementation methodology, for improving both quality and ease-of-use capability.

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