STMicroelectronics Puts SoC Integration into Fast Forward
Wireless Application Platform

Abstract
Time to market is STMicroelectronics number one business challenge. Market requirements evolve so rapidly and the time-to-market characteristics of its business are so demanding that the company has to continually step-up the pace with which it turns out new generations of chips. Chips such as the STi5516, an addition to the highly successful OMEGA family of set-box SoCs.

This SoC sets new standards of performance. Processor speed has more than doubled and the cache is quadrupled, providing faster response time for viewers and flexibility to the system. So, to get more SoCs to market faster - and less expensively - STMicroelectronics combined forces with Synopsys Professional Services to conceive a new flow for the SoC Bus Interconnect-based integration. They put it into action first with the company's STBus interconnect soft and configurable IP library within the coreAssembler platform.

Every SoC has to have a communications backbone interconnecting all the subsystems. And implementing that backbone can be a significant bottleneck in the SoC integration, depending on the system complexity. From spec to netlist, it can take up to two months to implement the communications backbone for a device with 80 million or more transistors.

The objective of the new methodology is straightforward. Make IP easy to implement and to integrate within a system. IP developers must deliver IP that can be reliably used by the integrator. First, the IP must be easy to configure for different target technologies and applications. That's why, increasingly, soft and configurable IP is the way to go.

Making IP faster and easier to integrate also means giving the integrator the means to rapidly assemble, synthesize, and verify the SoC. STMicroelectronics' pioneering approach, developed in collaboration with Synopsys, delivers a library of soft IP packages - called coreKits - that is complete with all the necessary integration aids.

The STBus Interconnect coreKit is an excellent example. The integrator builds the SoC interconnect backbone by doing system-level analysis utilizing SystemC™ models, simulating the subsystem and analyzing the system-level results. Once the system goals are met a set of configuration parameters are automatically generated and passed through coreAssembler to configure the sub-system components. Everything else is automated. Using a target library of base components, coreAssembler generates the configured, connected RTL view, a gate-level netlist, or both, in a matter of minutes. Eliminating the manual RTL coding not only saves time, it prevents errors and improves quality.

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