Hierarchical Integration and STA with ILMs Using PTSI

Abstract
As industry trends of larger gate sizes and smaller geometries continue, chip-level timing closure is becoming even more of a major obstacle in taping out a design. Static Timing Analysis (STA) run times and memory requirements increase, as gate sizes increase, and signal integrity issues are more apparent as geometries decrease. Signal integrity analysis using Primetime®-SI adds additional memory requirements to STA runs because complex signal integrity computations are preformed. ILM models allow sub-chips to be represented as an interface model that can be significantly smaller in gate size, thus reducing chip-level STA memory requirements and run times. This paper presents how ILM models were used in a real .13u hierarchical design for chip-level STA integration using Primetime-SI.

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