Formal Verification: Verification of an ECO-Intensive Hierarchical Design

Abstract
Tracking Formal Verification results becomes increasingly complicated with large, hierarchical designs, multi-site design teams, and ECO processes. As each hierarchical block progresses from RTL through synthesis, floorplanning, place & route and ECO's, the original design flow must be modified on a per-block basis. Some blocks may experience a netlist ECO and corresponding RTL change, but no re-synthesis, while other block-design flows remain intact. This paper describes a Formal Verification toolset which allows the design team to automatically track the verification flow of multiple blocks, at various design stages, with different design flows. This toolset was applied to a 2.6M gate, hierarchical ASIC, in an ECO-intensive design flow.

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