PTSI Methodology and Results for Hierarchical 2M gate ASIC

Abstract
Now that Signal Integrity Analysis (STA) is a required activity for processes .13µ and under, it is important for design teams to develop an accurate, predictable, and repeatable methodology for dealing with Signal Integrity issues. This paper presents the results of incorporating an SI methodology into a design flow, with emphasis in lessons learned.

It describes the issues related with the technology libraries, and discusses how this can make or break the flow. Then, it discusses the issue of tool setup. Unlike other tools (e.g., DC), where default values normally provide an adequate starting point for analysis, PrimeTime®-SI requires more fine-tuned setups to achieve accurate results, many of which are technology and design dependent. The paper describes the repair (ECO) process, compares it with alternative repair processes, closes with a lessons learned section, and discusses planned changes in flow for future projects.

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