SystemC™-Based Design of an IP Forwarding Chip with CoCentric® System Studio

Abstract
The ever-increasing complexity and heterogeneity of modern systems-on-chip (SoC) designs demand early consideration and exploration of architectural alternatives, which is hardly practicable on the low abstraction level of implementation models. In this paper, a system-level design methodology based on the SystemC 2.0 library is proposed, which enables the designer to reason about the architecture on a much higher level of abstraction. The goal of this methodology is to define system architectures, which provide sufficient performance, flexibility and power efficiency as required by demanding application domains -- wireless communications, broadband networking and multimedia applications. The methodology also provides capabilities for simulating multiple levels of abstraction simultaneously. This enables re-use of the simulation environment for functional verification and of the synthesizable implementation models against the abstract architecture model.

During an engagement with Synopsys Professional Services, this methodology is integrated into CoCentric® System Studio (CCSS) and applied to the development of a 2.5 GB IP forwarding chip with Quality-of-Service (QoS) support. In this paper we share our experiences with the latest SystemC 2.0-based features of CCSS -- used as a common design platform for abstract architecture modeling, profiling and hardware implementation. During the architecture exploration phase, we heavily employ the CCSS profiling capabilities to validate the performance of several architectural alternatives. Synopsys' Telecom Workbench serves as a functional verification tool throughout the complete design process.

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