|
Abstract The work done jointly by STM, Inc. and Synopsys, Inc. on the STBus Interconnect addresses the challenges associated with the re-use of soft IP. When incorporated into the packaging framework provided by Synopsys core tools solution, the soft IP can be maximally leveraged and meet a list of requirements defined in the Blue Book (reference for the implementation of Design Reuse within ST). By exploitation of the framework developed inside the Synopsys' tools, coreBuilder and coreConsultant, a design methodology for the implementation of a generic interconnect sub-system based on STBus protocol has been developed. Such methodology is based on the re-use of configurable soft IP so called "STBus interconnect" aiming to provide an integration platform for SoCs. STM designers have developed a library of STBus components, which have been packaged by Core Developers using coreBuilder. The effort of packaging is to provide a single entity, called coreKit, containing all of the information of the IP. The integrators of the IP can then simply load this coreKit and configure it using the friendly graphical interface provided by coreConsultant, to then obtain an RTL view and/or a gate-level netlist of the configured interconnect. The architectural inputs for the coreKit can be captured loading the System-Level Design configuration file, generated as a result of architectural exploration. The idea is to allow the designer to rapidly assemble, synthesize and verify an SoC through a new methodology which uses coreKits for each IP and for each bus in the system, together with the target library and generate a configured and connected RTL, together with the most appropriate synthesis strategy. All of this is part of an overall SoC flow that includes interactions with other tools such as: Physical Compiler®, Chip Architect, PrimeTime™, and more. |