Improving Timing Predictability for Soft Cores

Abstract
The complexity and immediacy of today's systems-on-chip (SoC) designs, determines the strategy of using soft IP cores for new SoC design projects within ST Microelectronics (ST ) Bristol. When delivering a soft IP core to a customer for physical implementation, a key parameter is the early confidence that physical implementation and timing closure are both feasible and predictable.

Historically, Synopsys ' Design Compiler® (DC) had been used to test this confidence, adding extra timing margins to allow for inherent optimism observed with this approach. However, as silicon geometries and clock periods shrink, this optimism has become an intolerable inaccuracy.

This issue is partly addressed by Synopsys' Physical Compiler® (PC) which unifies the synthesis and placement process. This methodology has provided core developers at ST Bristol with a more accurate early prediction of post-layout results. One barrier to adopting this flow was the requirement that a detailed design floorplan should be available early in the design process.

Minimal Physical Constraints (PC-PC) enables the auto-creation of a detailed floorplan with a few simple constraints. This has enabled the core developers to investigate the benefits of different floorplans and to predict the effect on the post-synthesis results, quickly and accurately.

This paper focuses on how PC-PC improves the design methodology and timing predictability for soft-core developers within ST Bristol.

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