Reference Methodology for Enabling Core-Based Design

Abstract
In order to fully enable core-based design for today's systems-on-chip (SoC) developments, the ability to quickly harden soft intellectual property (IP) and then accurately model the implementation is imperative. This approach gives the designer the flexibility of soft IP with the predictability and re-usability of hard IP.

Modeling soft IP at higher levels of abstraction not only enables faster time to market through IP re-use without re-verification, but it also has the added benefit of secure IP protection. A variety of models of the hardened IP are required to support a complete SoC design flow. The functional model is implementation independent, and can be created directly from the soft IP. Whereas the physical, timing, test and power models, are implementation dependent and therefore must be derived from a technology-specific implementation of the soft IP.

IP re-use without re-verification requires that these models be of a "sign-off" quality and should not compromise the ease with which the IP can be integrated into a system chip. In the interests of time to market and interoperability, these models should be easy to create and should comply with industry standards.

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