Implementation experience from a SystemC based design

Abstract
This paper details the methodology used for the implementation of a multi-million gates chip from RTL SystemC to gates.

It describes the SystemC based design methodology and guidelines for design partitioning and coding. It also describes an implementation flow using SystemC Compiler for ASIC synthesis, a SystemC & HDL co-verification environment and specific FPGA prototyping issues. The paper shares some of the results and lessons learned from the Synopsys Professional Service group's experience on customer designs implemented using SystemC. The paper will benefit the designers and verification engineers who use or plan to use SystemC RTL to implement their designs

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