A Practical Approach to Post-layout Timing Closure with Collapsed Clock Tree Annotation

Abstract
The Collapsed Clock Tree Annotation method is one of the commonly used clock tree back-annotation methods that has an advantage -- expanded clock trees can be back-annotated to an original netlist. However, the method has a drawback. The back-annotated clock tree insertion delays will be lost in post-layout design optimization when any cells in the clock trees are moved or sized. To solve this problem, a CTS annotation preservation approach has been developed. The approach has been successfully applied to timing closure of a number of ASIC designs.

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