Timing Closure of a High Performance and a Low-Power Generic DMA Controller

Abstract
This paper describes a number of timing closure techniques applied to a 210MHz & 150k gates generic DMA controller sub-chip designed to be embedded in various ASIC application chips in TI. The timing closure of the sub-chip was challenging due to multiple requirements of chip speed, clock distribution, power consumption and reliable sub-chip embedment. This paper, explains how we achieve timing closure of the sub-chip using Physical Compiler® (PC) for placement optimization. It describes in detail how to constrain clock distribution in PC to minimize clock insertion delays and how to maximize clock gating effects in order to reduce chip power consumption. Also included is how to reduce sub-chip modeling inaccuracy and risk of antenna violations at the top level where the sub-chip is embedded.

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