An Efficient Design Flow and Platform for SoC Design Using CoCentric® Tools

Abstract
The concept of the systems-on-chip (SoC) is creating many new challenges at all stages of design flow. The challenges include the modeling and verification of these SoCs as the complexity of designs increase day by day. To a large extent the target platforms used for the SoC design affect the productivity, as the requirements of the SoC design environment need to meet very complex performance objectives. Today's executable design platforms exist only at the Register Transfer (RT) Level which is too late in the design cycle and makes the simulation speed too slow.

Besides the platform, the modeling language used for the SoC design also plays an important role. The modeling language should exhibit powerful features for modeling and should support re-usable design descriptions. The underlying modeling language in the design flow referred here is SystemC™. SystemC is a modeling language based on C++, intended to enable system-level design and Intellectual Property exchange. The purpose of this paper is to briefly review the SystemC modeling concepts and how the new CoCentric design tools can be employed in today's system-level design. A design example is presented that demonstrates how the SystemC modeling can be used for the architecture explorations before fixing the final architecture. The paper also discusses how the CoCentric design tools help to have a complete design flow and thus satisfy the need for a SoC design platform. It also shows that the design platform bridges the gap to gates as the models can be synthesized to gates using the synthesis tool in the suggested platform.

The system-level design flow introduced, has been successfully used from defining the executable specifications at the functional level to the architecture explorations for an IPv4 Router Chip.

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