Virtual Architecture Mapping: A SystemC based Methodology for Architectural Exploration of System-on-Chip Designs

Abstract
The ever increasing complexity and heterogeneity of modern System-on-Chip designs demands early consideration and exploration of architectural alternatives, which is hardly practicable on the low abstraction level of implementation models. In this paper, a system level design methodology based on the SystemC 2.0 library is proposed, which enables the designer to reason about the architecture on a much higher level of abstraction. Goal of this methodology is to define a system architecture, which provides sufficient performance, flexibility and cost efficiency as required by demanding applications like broadband networking or wireless communications. The methodology also provides capabilities for co-simulating multiple levels of abstraction simultaneously. This enables reuse of the simulation environment for functional verification of synthesizable implementation models against the abstract architecture model. During a cooperation with Synopsys Professional Services, this methodology is applied to the development of a 2.5 GB IP forwarding chip with Quality-of-Service (QoS) support. In this paper we share our experiences of this real-life case-study with special emphasis on the architecture exploration phase, where several architectural alternatives are evaluated with respect to their impact on the system performance.

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